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AJvYcCUuElhavILzSBIF/vnFqXDyARcouCxYWfNmbHsvZgNWcxHmDIKOn+PQaZBMv+BcKx07Orsd0DDrWhBTge4/1xuEsF6qdmkybEfi+1ju X-Gm-Message-State: AOJu0YzFYx9XxgtfoJYb5RKfP7XkAucaTY5ORyTS7GAiZFgHWGHOxyDV LvC/8g7riTVeJvDrIRPkzEzKpKOBAGc0nU8TXJDeRfRI8H0Lu4dmY7tlXuit+OR1yYbHPlbAzu9 mRamWHX6uDXUXGu/7IA== X-Received: from ericchancf.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:4139]) (user=ericchancf job=sendgmr) by 2002:a05:6902:114d:b0:dc6:d2c8:6e50 with SMTP id p13-20020a056902114d00b00dc6d2c86e50mr105619ybu.7.1707864006063; Tue, 13 Feb 2024 14:40:06 -0800 (PST) Date: Tue, 13 Feb 2024 22:40:00 +0000 In-Reply-To: <20240213223810.2595804-1-ericchancf@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240213223810.2595804-1-ericchancf@google.com> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog Message-ID: <20240213224000.2597959-1-ericchancf@google.com> Subject: [PATCH v5 4/4] riscv/barrier: Resolve checkpatch.pl error From: Eric Chan To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, ericchancf@google.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790826971661536612 X-GMAIL-MSGID: 1790826971661536612 The past form of RISCV_FENCE would cause checkpatch.pl to issue error messages, the example is as follows: ERROR: space required after that ',' (ctx:VxV) +#define __atomic_acquire_fence() RISCV_FENCE(r,rw) ^ fix the remaining of RISCV_FENCE. Signed-off-by: Eric Chan --- arch/riscv/include/asm/barrier.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h index 4f4743d7440d..880b56d8480d 100644 --- a/arch/riscv/include/asm/barrier.h +++ b/arch/riscv/include/asm/barrier.h @@ -19,19 +19,19 @@ /* These barriers need to enforce ordering on both devices or memory. */ -#define __mb() RISCV_FENCE(iorw,iorw) -#define __rmb() RISCV_FENCE(ir,ir) -#define __wmb() RISCV_FENCE(ow,ow) +#define __mb() RISCV_FENCE(iorw, iorw) +#define __rmb() RISCV_FENCE(ir, ir) +#define __wmb() RISCV_FENCE(ow, ow) /* These barriers do not need to enforce ordering on devices, just memory. */ -#define __smp_mb() RISCV_FENCE(rw,rw) -#define __smp_rmb() RISCV_FENCE(r,r) -#define __smp_wmb() RISCV_FENCE(w,w) +#define __smp_mb() RISCV_FENCE(rw, rw) +#define __smp_rmb() RISCV_FENCE(r, r) +#define __smp_wmb() RISCV_FENCE(w, w) #define __smp_store_release(p, v) \ do { \ compiletime_assert_atomic_type(*p); \ - RISCV_FENCE(rw,w); \ + RISCV_FENCE(rw, w); \ WRITE_ONCE(*p, v); \ } while (0) @@ -39,7 +39,7 @@ do { \ ({ \ typeof(*p) ___p1 = READ_ONCE(*p); \ compiletime_assert_atomic_type(*p); \ - RISCV_FENCE(r,rw); \ + RISCV_FENCE(r, rw); \ ___p1; \ }) @@ -68,7 +68,7 @@ do { \ * instances the scheduler pairs this with an mb(), so nothing is necessary on * the new hart. */ -#define smp_mb__after_spinlock() RISCV_FENCE(iorw,iorw) +#define smp_mb__after_spinlock() RISCV_FENCE(iorw, iorw) #include