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AJvYcCWJB6s0uOWf/gL4yJ56gcBGsj937G41IEiLhVORwJ08yb2+9MSbW+R2yJ3Y0IBSTo4F7PbSyjxrafAEcRUQAK7Jn+lqXaYfaw+DW9ym X-Gm-Message-State: AOJu0Ywrtu06hc3SiTfjSGmGtJH3xxOisP1Sb0VqChUdlNs8AAbhqKgG WeErNsb5Yw1oBF+qtMDxekerIwi0zhBxJf01cC6tBBVLd4/IdG/3BLQT5yr1yBxsddq8YloJt9c 0ciyYuw4NoKvT/IPj4g== X-Received: from ericchancf.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:4139]) (user=ericchancf job=sendgmr) by 2002:a25:d842:0:b0:dc6:e8a7:fdba with SMTP id p63-20020a25d842000000b00dc6e8a7fdbamr161224ybg.4.1707863957363; Tue, 13 Feb 2024 14:39:17 -0800 (PST) Date: Tue, 13 Feb 2024 22:39:09 +0000 In-Reply-To: <20240213223810.2595804-1-ericchancf@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240213223810.2595804-1-ericchancf@google.com> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog Message-ID: <20240213223909.2596587-1-ericchancf@google.com> Subject: [PATCH v5 1/4] riscv/barrier: Define __{mb,rmb,wmb} From: Eric Chan To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, ericchancf@google.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790825174944164852 X-GMAIL-MSGID: 1790825174944164852 Introduce __{mb,rmb,wmb}, and rely on the generic definitions for {mb,rmb,wmb}. Although KCSAN is not yet support, it can be made more consistent with generic instrumentation. Signed-off-by: Eric Chan --- arch/riscv/include/asm/barrier.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h index 110752594228..4c49a8ff2c68 100644 --- a/arch/riscv/include/asm/barrier.h +++ b/arch/riscv/include/asm/barrier.h @@ -20,9 +20,9 @@ __asm__ __volatile__ ("fence " #p "," #s : : : "memory") /* These barriers need to enforce ordering on both devices or memory. */ -#define mb() RISCV_FENCE(iorw,iorw) -#define rmb() RISCV_FENCE(ir,ir) -#define wmb() RISCV_FENCE(ow,ow) +#define __mb() RISCV_FENCE(iorw,iorw) +#define __rmb() RISCV_FENCE(ir,ir) +#define __wmb() RISCV_FENCE(ow,ow) /* These barriers do not need to enforce ordering on devices, just memory. */ #define __smp_mb() RISCV_FENCE(rw,rw)