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AJvYcCV651hGpPeTVcv9W3WurymzRLY03ESpVNKhE5M4Wp0z/s3utp5agUIznykJxIjjnEv4Z18lLmA/W0RcR0TJpIlln40wxg0RUxeW4ka0 X-Gm-Message-State: AOJu0YwlFChgSOWzUSyGbPeUof8sy3Cdkht33Z4UQ8CSmHk6IjGEC/TA i+eTRAd8Wb6dW4k3okpHa2Y/ogdzWPNJfa69zZs8xbNv7rN1ZA+zt690/7Cjl+IGiJ8LkaaIaO2 SmY8vPbi2BeSuTBZySA== X-Received: from ericchancf.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:4139]) (user=ericchancf job=sendgmr) by 2002:a0d:d989:0:b0:607:8b76:4744 with SMTP id b131-20020a0dd989000000b006078b764744mr104441ywe.2.1707855107574; Tue, 13 Feb 2024 12:11:47 -0800 (PST) Date: Tue, 13 Feb 2024 20:11:41 +0000 In-Reply-To: <20240213200923.2547570-1-ericchancf@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240213200923.2547570-1-ericchancf@google.com> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog Message-ID: <20240213201141.2548566-1-ericchancf@google.com> Subject: [PATCH v4 1/4] riscv/barrier: Define __{mb,rmb,wmb} From: Eric Chan To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, ericchancf@google.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790815892868686533 X-GMAIL-MSGID: 1790815892868686533 Introduce __{mb,rmb,wmb}, and rely on the generic definitions for {mb,rmb,wmb}. Although KCSAN is not yet support, it can be made more consistent with generic instrumentation. Signed-off-by: Eric Chan --- v3 -> v4: fix commit message weird line breaks arch/riscv/include/asm/barrier.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.43.0.687.g38aa6559b0-goog diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h index 110752594228..4c49a8ff2c68 100644 --- a/arch/riscv/include/asm/barrier.h +++ b/arch/riscv/include/asm/barrier.h @@ -20,9 +20,9 @@ __asm__ __volatile__ ("fence " #p "," #s : : : "memory") /* These barriers need to enforce ordering on both devices or memory. */ -#define mb() RISCV_FENCE(iorw,iorw) -#define rmb() RISCV_FENCE(ir,ir) -#define wmb() RISCV_FENCE(ow,ow) +#define __mb() RISCV_FENCE(iorw,iorw) +#define __rmb() RISCV_FENCE(ir,ir) +#define __wmb() RISCV_FENCE(ow,ow) /* These barriers do not need to enforce ordering on devices, just memory. */ #define __smp_mb() RISCV_FENCE(rw,rw)