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AJvYcCV/ROWtHSVL4gthMIudCU9Sfqu99ATwDZKFdrUkPnRSFTc7YlOjKyjNWj/Wj1NDZG1JR8NlRwCcGKsnyFzzTmCLTf0TJ3i6zducMOMx X-Gm-Message-State: AOJu0YxHsC5TMGppArQDlIUOsTy1LxEx2PZqgBo3Waz2mJ2O47js7N8a HzZ6Q/QXAI40Y4Z4fdBRcPNhdmNgd/AApzfJiosA7s919FiBmz0p1+7Gc5+KNlzHb/hjbnaH558 5khiWpSmYRn5sWra30w== X-Received: from ericchancf.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:4139]) (user=ericchancf job=sendgmr) by 2002:a81:920c:0:b0:5ff:6ec3:b8da with SMTP id j12-20020a81920c000000b005ff6ec3b8damr564874ywg.1.1707834542765; Tue, 13 Feb 2024 06:29:02 -0800 (PST) Date: Tue, 13 Feb 2024 14:28:56 +0000 In-Reply-To: <20240213142632.2415127-1-ericchancf@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240213142632.2415127-1-ericchancf@google.com> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog Message-ID: <20240213142856.2416073-1-ericchancf@google.com> Subject: [PATCH v3 1/4] riscv/barrier: Define __{mb,rmb,wmb} From: Eric Chan To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, ericchancf@google.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790794346249958904 X-GMAIL-MSGID: 1790794346249958904 Introduce __{mb,rmb,wmb}, and rely on the generic definitions for {mb,rmb,wmb}. Although KCSAN is not yet support, it can be made more consistent with generic instrumentation. Signed-off-by: Eric Chan --- arch/riscv/include/asm/barrier.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h index 110752594228..4c49a8ff2c68 100644 --- a/arch/riscv/include/asm/barrier.h +++ b/arch/riscv/include/asm/barrier.h @@ -20,9 +20,9 @@ __asm__ __volatile__ ("fence " #p "," #s : : : "memory") /* These barriers need to enforce ordering on both devices or memory. */ -#define mb() RISCV_FENCE(iorw,iorw) -#define rmb() RISCV_FENCE(ir,ir) -#define wmb() RISCV_FENCE(ow,ow) +#define __mb() RISCV_FENCE(iorw,iorw) +#define __rmb() RISCV_FENCE(ir,ir) +#define __wmb() RISCV_FENCE(ow,ow) /* These barriers do not need to enforce ordering on devices, just memory. */ #define __smp_mb() RISCV_FENCE(rw,rw)