Message ID | 20240213-xilinx_ecc-v8-1-8d75f8b80771@pengutronix.de |
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State | New |
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Miller" <davem@davemloft.net>, Eric Dumazet <edumazet@google.com>, Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Michal Simek <michal.simek@amd.com> Cc: linux-can@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Srinivas Goud <srinivas.goud@amd.com>, Conor Dooley <conor.dooley@microchip.com> X-Mailer: b4 0.13-dev-f0463 X-Developer-Signature: v=1; a=openpgp-sha256; l=1349; i=mkl@pengutronix.de; h=from:subject:message-id; bh=uqD/3nX7Gc5Q4vTRKA4laTqfp7s7VuC5z/kwrN2bMWY=; b=owEBbQGS/pANAwAKASg4oj56LbxvAcsmYgBly0Y/BOLEdRZtIEm+EERI1EFQyFPmgKcG9skzd QVybQLpe6mJATMEAAEKAB0WIQRQQLqG4LYE3Sm8Pl8oOKI+ei28bwUCZctGPwAKCRAoOKI+ei28 b7BRB/9MgnMUIuGRaV4u1Tu0F6FYYyXfLjCpZ4OIuNgTZRZGktoKJmk/cj26LSfI+d+6sovipjB f36bK63tuMtpA28Of2GCME1KYAfYJlO1aZLbzrIJAGG+1t8O04ifSeK7JY4D6RbY9fx5m2+4Sqz 9Jxsz0LpBMLOujUCWHUKcXnhwO05M06PRGLJWtX6rFKDodTJfKaVGFj40pzMbhIBrS5InVRHvvO FoNdka0r4r5bdPWEkyw8WEja1k/f2D62nAI8z6Ts58NdXLSs1hJmwxMXvv8HeSjySvWnnYoyrLH Uc6dLQcE2qr5QZtvCva+rge3nYd/Y55zfSdHhSa2XppDkPSb X-Developer-Key: i=mkl@pengutronix.de; a=openpgp; fpr=C1400BA0B3989E6FBC7D5B5C2B5EE211C58AEA54 X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: mkl@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790779785165545078 X-GMAIL-MSGID: 1790779785165545078 |
Series |
Add ECC feature support to Tx and Rx FIFOs for Xilinx CAN Controller.
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Commit Message
Marc Kleine-Budde
Feb. 13, 2024, 10:36 a.m. UTC
From: Srinivas Goud <srinivas.goud@amd.com> ECC feature added to CAN TX_OL, TX_TL and RX FIFOs of Xilinx AXI CAN Controller. ECC is an IP configuration option where counter registers are added in IP for 1bit/2bit ECC errors. 'xlnx,has-ecc' is an optional property and added to Xilinx AXI CAN Controller node if ECC block enabled in the HW Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Srinivas Goud <srinivas.goud@amd.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> --- Documentation/devicetree/bindings/net/can/xilinx,can.yaml | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml index 64d57c343e6f..8d4e5af6fd6c 100644 --- a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml +++ b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml @@ -49,6 +49,10 @@ properties: resets: maxItems: 1 + xlnx,has-ecc: + $ref: /schemas/types.yaml#/definitions/flag + description: CAN TX_OL, TX_TL and RX FIFOs have ECC support(AXI CAN) + required: - compatible - reg @@ -137,6 +141,7 @@ examples: interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; + xlnx,has-ecc; }; - |