diff mbox series

[2/2] pinctrl: qcom: sm8450: Add pll_clk to pin group 98 for SM8475

Message ID 20240212191046.77013-3-danila@jiaxyga.com
State New
Headers
Series pinctrl: qcom: Add SM8475 support |

Commit Message

Danila Tikhonov Feb. 12, 2024, 7:10 p.m. UTC 
  Add pll_clk to pin group 98 for compatibility with SM8475.

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
---
 drivers/pinctrl/qcom/pinctrl-sm8450.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Krzysztof Kozlowski Feb. 13, 2024, 8:31 a.m. UTC | #1 
On 12/02/2024 20:10, Danila Tikhonov wrote:
> Add pll_clk to pin group 98 for compatibility with SM8475.

I don't understand this. What compatibility? Is it valid on SM8450? Ifi
so, then this would be fix. If not, then you just introduced incorrect
group for SM8450 and called it compatibility.

> 
> Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
> ---
>  drivers/pinctrl/qcom/pinctrl-sm8450.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450.c b/drivers/pinctrl/qcom/pinctrl-sm8450.c
> index 617286711695..45ac8e72c1c7 100644
> --- a/drivers/pinctrl/qcom/pinctrl-sm8450.c
> +++ b/drivers/pinctrl/qcom/pinctrl-sm8450.c
> @@ -957,7 +957,7 @@ static const char * const pll_bist_groups[] = {
>  };
>  
>  static const char * const pll_clk_groups[] = {
> -	"gpio107",
> +	"gpio98", "gpio107",


Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450.c b/drivers/pinctrl/qcom/pinctrl-sm8450.c
index 617286711695..45ac8e72c1c7 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8450.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8450.c
@@ -957,7 +957,7 @@  static const char * const pll_bist_groups[] = {
 };
 
 static const char * const pll_clk_groups[] = {
-	"gpio107",
+	"gpio98", "gpio107",
 };
 
 static const char * const pri_mi2s_groups[] = {
@@ -1511,7 +1511,7 @@  static const struct msm_pingroup sm8450_groups[] = {
 	[95] = PINGROUP(95, pcie0_clkreqn, cmu_rng, phase_flag, _, _, _, _, _, _),
 	[96] = PINGROUP(96, cmu_rng, phase_flag, _, _, _, _, _, _, _),
 	[97] = PINGROUP(97, cmu_rng, phase_flag, _, _, _, _, _, _, _),
-	[98] = PINGROUP(98, pcie1_clkreqn, phase_flag, _, _, _, _, _, _, _),
+	[98] = PINGROUP(98, pcie1_clkreqn, phase_flag, pll_clk, _, _, _, _, _, _),
 	[99] = PINGROUP(99, phase_flag, cri_trng, _, _, _, _, _, _, _),
 	[100] = PINGROUP(100, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
 	[101] = PINGROUP(101, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),