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Mon, 12 Feb 2024 18:52:19 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 3B9C9257A8E; Mon, 12 Feb 2024 18:51:37 +0100 (CET) Received: from localhost (10.201.22.200) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 12 Feb 2024 18:51:36 +0100 From: Christophe Kerello To: , , , , , , CC: , , , , Christophe Kerello Subject: [PATCH 12/12] mtd: rawnand: stm32_fmc2: update the driver to support revision 2 Date: Mon, 12 Feb 2024 18:48:22 +0100 Message-ID: <20240212174822.77734-13-christophe.kerello@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240212174822.77734-1-christophe.kerello@foss.st.com> References: <20240212174822.77734-1-christophe.kerello@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-12_15,2024-02-12_03,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790716705644354924 X-GMAIL-MSGID: 1790716705644354924 Add the support of the revision 2 of FMC2 IP. For the NAND controller, the bit used to enable the IP has moved. Signed-off-by: Christophe Kerello --- drivers/mtd/nand/raw/stm32_fmc2_nand.c | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c index d71ec12cd5b1..877255b0d0fc 100644 --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c @@ -54,6 +54,7 @@ /* FMC2 Controller Registers */ #define FMC2_BCR1 0x0 +#define FMC2_CFGR 0x20 #define FMC2_PCR 0x80 #define FMC2_SR 0x84 #define FMC2_PMEM 0x88 @@ -83,10 +84,14 @@ #define FMC2_BCHDSR2 0x284 #define FMC2_BCHDSR3 0x288 #define FMC2_BCHDSR4 0x28c +#define FMC2_VERR 0x3f4 /* Register: FMC2_BCR1 */ #define FMC2_BCR1_FMC2EN BIT(31) +/* Register: FMC2_CFGR */ +#define FMC2_CFGR_FMC2EN BIT(31) + /* Register: FMC2_PCR */ #define FMC2_PCR_PWAITEN BIT(1) #define FMC2_PCR_PBKEN BIT(2) @@ -208,6 +213,10 @@ #define FMC2_BCHDSR4_EBP7 GENMASK(12, 0) #define FMC2_BCHDSR4_EBP8 GENMASK(28, 16) +/* Register: FMC2_VERR */ +#define FMC2_VERR_MAJREV GENMASK(7, 4) +#define FMC2_VERR_MAJREV_2 2 + enum stm32_fmc2_ecc { FMC2_ECC_HAM = 1, FMC2_ECC_BCH4 = 4, @@ -1397,9 +1406,20 @@ static void stm32_fmc2_nfc_init(struct stm32_fmc2_nfc *nfc) pcr |= FIELD_PREP(FMC2_PCR_TAR, FMC2_PCR_TAR_DEFAULT); /* Enable FMC2 controller */ - if (nfc->dev == nfc->cdev) - regmap_update_bits(nfc->regmap, FMC2_BCR1, - FMC2_BCR1_FMC2EN, FMC2_BCR1_FMC2EN); + if (nfc->dev == nfc->cdev) { + u32 verr; + u8 majrev; + + regmap_read(nfc->regmap, FMC2_VERR, &verr); + majrev = FIELD_GET(FMC2_VERR_MAJREV, verr); + + if (majrev < FMC2_VERR_MAJREV_2) + regmap_update_bits(nfc->regmap, FMC2_BCR1, + FMC2_BCR1_FMC2EN, FMC2_BCR1_FMC2EN); + else + regmap_update_bits(nfc->regmap, FMC2_CFGR, + FMC2_CFGR_FMC2EN, FMC2_CFGR_FMC2EN); + } regmap_write(nfc->regmap, FMC2_PCR, pcr); regmap_write(nfc->regmap, FMC2_PMEM, FMC2_PMEM_DEFAULT);