Message ID | 20240212-mt8186-ssusb-domain-clk-fix-v1-1-26cb98746aa3@collabora.com |
---|---|
State | New |
Headers |
Return-Path: <linux-kernel+bounces-62398-ouuuleilei=gmail.com@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:bc8a:b0:106:860b:bbdd with SMTP id dn10csp179409dyb; Mon, 12 Feb 2024 13:33:56 -0800 (PST) X-Google-Smtp-Source: AGHT+IEDXUDJ2c2KIQsuirOvexY/jv04JlvEqjBTfMiBevFHQFlSXdalmUtXqkcKO4rhYoSmro1b X-Received: by 2002:a17:902:6e10:b0:1d9:11bd:e212 with SMTP id u16-20020a1709026e1000b001d911bde212mr6445449plk.60.1707773635835; Mon, 12 Feb 2024 13:33:55 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707773635; cv=pass; d=google.com; s=arc-20160816; b=IJxecag6T9J3bpKHqGCotZnVIRvz8Z0qp2c/RQQ3Y2bJInXB0AadUFSUcPiT0Bh3CZ b3ucns1NGZw0e+5uK2Tul4TVWABZiKQxm2f7kfZweo433fqxWMZNWzzy+u8KzwI/HaKC wAZqJRq6iJyjUxnjKYoEl+yIFEswz873BX5dPElyjBOhpkLUZtbF3IgObTeYx5sJ1Do/ 6M0XvoKJ/LB47dtx9R+RZi0mz589UzEFdc/nOdKmYhmaJ4m1jtyYo6g6tcJ9hUJCh3Pv nbMIaJ7m8UQ1aY3nLPtilow8aPk6giMoQQ4I5Pk57e+nw9X6iiHLoWL9D3iaJAIvOqV1 UuTQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:message-id:content-transfer-encoding:mime-version :list-unsubscribe:list-subscribe:list-id:precedence:subject:date :from:dkim-signature; bh=xLgB39N3TSdl3rr2Xu7xXsmbw+8nItqyRO4tusEPd7U=; fh=DLtmzUpIR7j4iqECdxoJmAYUh7cDofyttMggDU/y9Bo=; b=jKYck2c/62t21o9GPrbz7+uQTf98Senc8+JftzHK6q7r4N+JLJLgjgl2StoudU2yK6 uFJQGzPba45gVAIcJHnSDnCqJRzxtRfqe/BN45WAFZmjOhRDvMnbyusirCZAhQ1lbq7s 37X6eCMH+Xre3jKEBVUIY63yXY+8h8kxe4qmCnM5pE8QpuPOk/dlBL9L7CSmJ2zGQk+O V334sgK4rwB04YwbO5q3vX9Qpq+9J0iX9LpktX7X4EIeyzOZno1njYo3e2FoalGMMEP9 5GpvEDCwSBXPKsammWxZEGRkd+tWjdITH5tS4nR7uoNUFGIo19g48m5FKYxgVLj90aeC 1gWw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=eFEm9K9Q; arc=pass (i=1 spf=pass spfdomain=collabora.com dkim=pass dkdomain=collabora.com dmarc=pass fromdomain=collabora.com); spf=pass (google.com: domain of linux-kernel+bounces-62398-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-62398-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com X-Forwarded-Encrypted: i=2; AJvYcCXG38PTfzuV4cJeM0MQczSaX1dXs4xeF9kJDHIL1NzlcHPtj3WVsyrDYBhMF99XeLwRyRwhWAtSQmSXQCgtjUGP/v+gdQ== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. [139.178.88.99]) by mx.google.com with ESMTPS id f12-20020a170902684c00b001da1efbd32asi13593pln.443.2024.02.12.13.33.55 for <ouuuleilei@gmail.com> (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Feb 2024 13:33:55 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-62398-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) client-ip=139.178.88.99; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=eFEm9K9Q; arc=pass (i=1 spf=pass spfdomain=collabora.com dkim=pass dkdomain=collabora.com dmarc=pass fromdomain=collabora.com); spf=pass (google.com: domain of linux-kernel+bounces-62398-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-62398-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id 9CB1F28505D for <ouuuleilei@gmail.com>; Mon, 12 Feb 2024 21:33:55 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 242A64D9FF; Mon, 12 Feb 2024 21:33:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="eFEm9K9Q" Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A5474EB43; Mon, 12 Feb 2024 21:33:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707773589; cv=none; b=VaPtDwbx6rP5mj7HYz1Ed3bFQu8iTPlWP0KRo6fldS3wtGxbggeo89Mh03ClcfNQP4Mce95zZVa8i+AqOjwd3K0aQwoZkJE1JdMNQfzGwy/mFXcNuPZAfEnOOfr1NmTdct6/xIEbEW0CSNT59ZBIMuTVdWpNqznr7g6K6Q++o14= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707773589; c=relaxed/simple; bh=uL2VF2cuPmkBo5+K9BYWgnyBPmjt/fB97ck51Phazr0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:To:Cc; b=D8mIM9d8RxT/0yRcm1MyxM3HnN0nnYmhUWIRFqQWkw7gWQlguIky7gbZC0dxz7+C8X0QCgRt8fC7bu6iIkPsJczwRA8V6qJbdkASeB4qA8Aw6TUO+4e2ztXhXv1UjbWxeOpWs6O4axWzNf+1qu2o/y5ysr9a+iCX53+ffCPB6Jk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=eFEm9K9Q; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1707773584; bh=uL2VF2cuPmkBo5+K9BYWgnyBPmjt/fB97ck51Phazr0=; h=From:Date:Subject:To:Cc:From; b=eFEm9K9QpelSO+d7WVm/xhJd8+qlJVpl+tnlGZsb8vckGa1tyIHVKBBxNBVdg5h3g 3xn2YJbATiyjnp+W1pamAs+m/yX7gjozx61rrNayDWpJYrw3Mm+FAxyt0f8gSibUTl qiGnQfhI+E8SQMHzYAK+vBlQHnYB7bbVTYnW9KGqXIytwVtQnB045arzq3sWOmOPKf +CP8ZGVO7vSS1mcVCImsZCKPeOTOOYrmVnN74ekEC0A65d7GaICBVkMBcLCKWe5rb4 F3i/YS4CiM3Sm0Ddj0/LX3jrrkpA3LtymZwNI9RTJ2/HmANT99dOlTnnyrZmWQzK8R a1cANRtoq1K7Q== Received: from [192.168.1.38] (zone.collabora.co.uk [167.235.23.81]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madrid.collaboradmins.com (Postfix) with ESMTPSA id 9619237813D5; Mon, 12 Feb 2024 21:33:01 +0000 (UTC) From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= <nfraprado@collabora.com> Date: Mon, 12 Feb 2024 16:32:44 -0500 Subject: [PATCH] arm64: dts: mediatek: mt8186: Add missing clocks to ssusb power domains Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: <linux-kernel.vger.kernel.org> List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-Id: <20240212-mt8186-ssusb-domain-clk-fix-v1-1-26cb98746aa3@collabora.com> X-B4-Tracking: v=1; b=H4sIAHuOymUC/x3MQQqDMBBA0avIrDuQRJHUq5QuYjLRoRpLRkUQ7 25w+f7inyCUmQS66oRMOwsvqUC/KvCjSwMhh2IwyjTKaIPzarVtUWSTHsMyO07opx9GPtC1b03 kbd3EAOXwz1Tyc/98r+sGwYRV3W0AAAA= To: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>, Matthias Brugger <matthias.bgg@gmail.com> Cc: Chen-Yu Tsai <wenst@chromium.org>, Eugen Hristev <eugen.hristev@collabora.com>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Allen-KH Cheng <allen-kh.cheng@mediatek.com>, kernel@collabora.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= <nfraprado@collabora.com> X-Mailer: b4 0.12.4 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790730447807023796 X-GMAIL-MSGID: 1790730447807023796 |
Series |
arm64: dts: mediatek: mt8186: Add missing clocks to ssusb power domains
|
|
Commit Message
Nícolas F. R. A. Prado
Feb. 12, 2024, 9:32 p.m. UTC
The ssusb power domains currently don't list any clocks, despite
depending on some, and thus rely on the bootloader leaving the required
clocks on in order to work.
When booting with the upstream arm64 defconfig, the power domain
controller will defer probe until modules have loaded since it has an
indirect dependency on CONFIG_MTK_CMDQ, which is configured as a module.
However at the point where modules are loaded, unused clocks are also
disabled, causing the ssusb domains to fail to be enabled and
consequently the controller to fail probe:
mtk-power-controller 10006000.syscon:power-controller: /soc/syscon@10006000/power-controller/power-domain@4: failed to power on domain: -110
mtk-power-controller: probe of 10006000.syscon:power-controller failed with error -110
Add the missing clocks to the ssusb power domains so the power
controller can boot without relying on bootloader state.
Fixes: d9e43c1e7a38 ("arm64: dts: mt8186: Add power domains controller")
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
---
base-commit: 2ae0a045e6814c8c1d676d6153c605a65746aa29
change-id: 20240212-mt8186-ssusb-domain-clk-fix-a691eec834fd
Best regards,
Comments
On Mon, Feb 12, 2024 at 04:32:44PM -0500, Nícolas F. R. A. Prado wrote: > The ssusb power domains currently don't list any clocks, despite > depending on some, and thus rely on the bootloader leaving the required > clocks on in order to work. > > When booting with the upstream arm64 defconfig, the power domain > controller will defer probe until modules have loaded since it has an > indirect dependency on CONFIG_MTK_CMDQ, which is configured as a module. > However at the point where modules are loaded, unused clocks are also > disabled, causing the ssusb domains to fail to be enabled and > consequently the controller to fail probe: > > mtk-power-controller 10006000.syscon:power-controller: /soc/syscon@10006000/power-controller/power-domain@4: failed to power on domain: -110 > mtk-power-controller: probe of 10006000.syscon:power-controller failed with error -110 > > Add the missing clocks to the ssusb power domains so the power > controller can boot without relying on bootloader state. > > Fixes: d9e43c1e7a38 ("arm64: dts: mt8186: Add power domains controller") > Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> > --- > arch/arm64/boot/dts/mediatek/mt8186.dtsi | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi > index adaf5e57fac5..02f33ec3cbd3 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi > @@ -931,11 +931,19 @@ power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP { > > power-domain@MT8186_POWER_DOMAIN_SSUSB { > reg = <MT8186_POWER_DOMAIN_SSUSB>; > + clocks = <&topckgen CLK_TOP_USB_TOP>, > + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, > + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>; > + clock-names = "sys_ck", "ref_ck", "xhci_ck"; > #power-domain-cells = <0>; > }; > > power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 { > reg = <MT8186_POWER_DOMAIN_SSUSB_P1>; > + clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, > + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, > + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>; > + clock-names = "sys_ck", "ref_ck", "xhci_ck"; I forgot to mention this here, but the XHCI clock wasn't needed to get the power domains to work per se, but leaving it out caused issues when probing the mtu3 devices: <3>[ 15.431506] mtu3 11201000.usb: clks of sts1 are not stable! <3>[ 15.443965] mtu3 11201000.usb: device enable failed -110 <3>[ 15.454306] mtu3 11201000.usb: mtu3 hw init failed:-110 <3>[ 15.463865] mtu3 11201000.usb: failed to initialize gadget <4>[ 15.477890] mtu3: probe of 11201000.usb failed with error -110 <3>[ 15.514603] mtu3 11281000.usb: clks of sts1 are not stable! <3>[ 15.525239] mtu3 11281000.usb: device enable failed -110 <3>[ 15.614174] mtu3 11281000.usb: mtu3 hw init failed:-110 <3>[ 15.619647] mtu3 11281000.usb: failed to initialize gadget <4>[ 15.630623] mtu3: probe of 11281000.usb failed with error -110 Not sure if this issue should be handled separately (maybe the mtu3 device should enable the XHCI clock?), but I opted to include the clock here to get boot working for this device at once. Thanks, Nícolas
Il 12/02/24 22:53, Nícolas F. R. A. Prado ha scritto: > On Mon, Feb 12, 2024 at 04:32:44PM -0500, Nícolas F. R. A. Prado wrote: >> The ssusb power domains currently don't list any clocks, despite >> depending on some, and thus rely on the bootloader leaving the required >> clocks on in order to work. >> >> When booting with the upstream arm64 defconfig, the power domain >> controller will defer probe until modules have loaded since it has an >> indirect dependency on CONFIG_MTK_CMDQ, which is configured as a module. >> However at the point where modules are loaded, unused clocks are also >> disabled, causing the ssusb domains to fail to be enabled and >> consequently the controller to fail probe: >> >> mtk-power-controller 10006000.syscon:power-controller: /soc/syscon@10006000/power-controller/power-domain@4: failed to power on domain: -110 >> mtk-power-controller: probe of 10006000.syscon:power-controller failed with error -110 >> >> Add the missing clocks to the ssusb power domains so the power >> controller can boot without relying on bootloader state. >> >> Fixes: d9e43c1e7a38 ("arm64: dts: mt8186: Add power domains controller") >> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> >> --- >> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 8 ++++++++ >> 1 file changed, 8 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi >> index adaf5e57fac5..02f33ec3cbd3 100644 >> --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi >> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi >> @@ -931,11 +931,19 @@ power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP { >> >> power-domain@MT8186_POWER_DOMAIN_SSUSB { >> reg = <MT8186_POWER_DOMAIN_SSUSB>; >> + clocks = <&topckgen CLK_TOP_USB_TOP>, >> + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, >> + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>; >> + clock-names = "sys_ck", "ref_ck", "xhci_ck"; >> #power-domain-cells = <0>; >> }; >> >> power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 { >> reg = <MT8186_POWER_DOMAIN_SSUSB_P1>; >> + clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, >> + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, >> + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>; >> + clock-names = "sys_ck", "ref_ck", "xhci_ck"; > > I forgot to mention this here, but the XHCI clock wasn't needed to get the power > domains to work per se, but leaving it out caused issues when probing the mtu3 > devices: > <3>[ 15.431506] mtu3 11201000.usb: clks of sts1 are not stable! > <3>[ 15.443965] mtu3 11201000.usb: device enable failed -110 > <3>[ 15.454306] mtu3 11201000.usb: mtu3 hw init failed:-110 > <3>[ 15.463865] mtu3 11201000.usb: failed to initialize gadget > <4>[ 15.477890] mtu3: probe of 11201000.usb failed with error -110 > > <3>[ 15.514603] mtu3 11281000.usb: clks of sts1 are not stable! > <3>[ 15.525239] mtu3 11281000.usb: device enable failed -110 > <3>[ 15.614174] mtu3 11281000.usb: mtu3 hw init failed:-110 > <3>[ 15.619647] mtu3 11281000.usb: failed to initialize gadget > <4>[ 15.630623] mtu3: probe of 11281000.usb failed with error -110 > > Not sure if this issue should be handled separately (maybe the mtu3 device > should enable the XHCI clock?), but I opted to include the clock here to get > boot working for this device at once. > Hey Nicolas, As you just said: having the XHCI clock in the power domain is wrong :-) Almost comically, the MTU3 binding already supports having a XHCI clock named "xhci_ck" after "dma_ck"... so the solution is to add the TOP_XHCI clock in the mtu3 node and that's it. Do not remove it from the children. mtu3-node-at-somewhere { clocks = <&topckgen CLK_TOP_USB_TOP>, <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, <&infracfg_ao CLK_INFRA_AO_ICUSB>, <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>; clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; } Waiting for a v2... Cheers, Angelo
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index adaf5e57fac5..02f33ec3cbd3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -931,11 +931,19 @@ power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP { power-domain@MT8186_POWER_DOMAIN_SSUSB { reg = <MT8186_POWER_DOMAIN_SSUSB>; + clocks = <&topckgen CLK_TOP_USB_TOP>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>; + clock-names = "sys_ck", "ref_ck", "xhci_ck"; #power-domain-cells = <0>; }; power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 { reg = <MT8186_POWER_DOMAIN_SSUSB_P1>; + clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>; + clock-names = "sys_ck", "ref_ck", "xhci_ck"; #power-domain-cells = <0>; };