From patchwork Mon Feb 12 13:44:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 199846 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp2459144dyd; Mon, 12 Feb 2024 06:23:59 -0800 (PST) X-Google-Smtp-Source: AGHT+IHCI+KWgHTBoQWRnMJ5RbcdXHJup9XUaaFLGuNJC4sWUGxs5BOhC/MpjHcs5auPoxnLz2qf X-Received: by 2002:a17:902:e74f:b0:1d7:5c60:f4f5 with SMTP id p15-20020a170902e74f00b001d75c60f4f5mr9686060plf.16.1707747839087; Mon, 12 Feb 2024 06:23:59 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707747839; cv=pass; d=google.com; s=arc-20160816; b=QRPBDTCejAXfAAsDnVqh3wD0fb/F6MleD2fatqYHmgssmlRCGzZXAvkh0JMfN2lFLa aBNmJjfKhk4bAgSeSwHql7cQTpawr5SscyLh7/JlhpCmG9OraxiZb/3vyOBDEM/7QH8D E6mt9hhXB/STG8p2gIq/VHzkiWIrtN7MUTgGoiuoZsmQUfVyBrcXB1CjoNWlODmTkU9A x9TIXeZXnZp3ZnP00y0Ncm1M8RA/d950chcS6QalrN/DdQfwaynMFxUIcdQfvp2cEOQq qmpLWAlepYyciCOcZTYs26Ia+EcFt/mo3etmR9Y0HJ7WTNfmq699YI5TIuQlsC/Z6SQV l7ug== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=FcFUqpSnnhPRAS/CSWnN37MHwsy8eP/c7jhpSXCs+BM=; fh=duCOPbxnmtD0bMqeVPEQYHyZmaPKLbtiVr1pAb93MRA=; b=Ol8whep0k6PfaxHgiQQB5JpN2cXN6NOiptBh1RhYy8EXa6BAg94cLhrhutxP7B5ujg hIJZKFRutBgtTzerRxwdjvkfMbZZvgAgnI69Ss7IHrutLtTn6p5dCD4SH6G+n8seA+4d ns1PKr/77b7D0YbJtfVzAYZpULmfA+3TyrtvwldCXmuEAoT/GKQJ1Jc8ooPr6Q+2mydn JWu8J4/O/zm0i9pJizSt+JB2vRjekGPm49aXBCN2v9yTRs2dgb0ymrYLOfh3dvl4nPyd UucQmEKyhKrZT9L4G/IlQNYOcIuEgN8o4P4wCavo/CoA8mGJVCtHyilN2s7GIXB6KOyd +Zbg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=m8wPylns; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-61732-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-61732-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com X-Forwarded-Encrypted: i=2; AJvYcCUxlVcD5c6D3vOyTWmRTbuPEcyH2msmuIp1epYaE/2CutBLpcWG0vL7SS9Q/tdUMwUbHSyGbPv89f8L88DouvIvo3uJBQ== Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. [2604:1380:40f1:3f00::1]) by mx.google.com with ESMTPS id jh2-20020a170903328200b001d7204a84ddsi314833plb.499.2024.02.12.06.23.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Feb 2024 06:23:59 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-61732-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) client-ip=2604:1380:40f1:3f00::1; Authentication-Results: mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=m8wPylns; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-61732-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-61732-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sy.mirrors.kernel.org (Postfix) with ESMTPS id BCA7AB24816 for ; Mon, 12 Feb 2024 13:51:36 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1196446542; Mon, 12 Feb 2024 13:44:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="m8wPylns" Received: from relay9-d.mail.gandi.net (relay9-d.mail.gandi.net [217.70.183.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C5B183D571; Mon, 12 Feb 2024 13:44:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.199 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707745481; cv=none; b=G0rbnUPhmzc4MmGM8mxae5fl84rDdFGtErNEpffATyiB3g4XpRID5gI8of5xGxDu18FmqS6s4hk/uWu3WrpkK/tckgOK/nYmG/ok9IfI5mlnqoDCNjKNW54SN92kqjpHjZAhg3t4NDHCn/34sGGkFd8DuLG/4uxbkDc6omfmMUM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707745481; c=relaxed/simple; bh=42b7G1ZWbG/3VuTtt/2iBwWHkysD3NSYhwEdaDARIwo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=e64umd/JYv2PiyCLZRA3Txu649uU/sOiBivuqTG2EKdgqOQYq+OEMP6uFElLPSwi2PEZ3670PFKl60NDoKtZ7sitpn0L41/n0Jf5M8ckfboMm8815uW6bLavno//eWjA3BojhvPrqfhY7iUQ7UWcbGfH82tprM5Hba1esr8i9LY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=m8wPylns; arc=none smtp.client-ip=217.70.183.199 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Received: by mail.gandi.net (Postfix) with ESMTPSA id 32270FF80A; Mon, 12 Feb 2024 13:44:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1707745477; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=FcFUqpSnnhPRAS/CSWnN37MHwsy8eP/c7jhpSXCs+BM=; b=m8wPylnsEuPb3HFEHxoXGVrvA3luLSdYElwowgJjp5b4/JcRzu3nvCI18/DlzEI1k/YYmU AzV8w7AIEdzUtpa2vPmh3zGae82sT165EC8B4hyUHlKK7xHA7AinfZGBj+xHOe0Bq2sZlG k7mWB8HInhw/MhdDHIlLXKnye+SFMyp/BjYfCgVW23tZRKOJ0OjeFZNlqLWB5qjrq8nPDW +3CnhL5KcnOVGyh8uoDtZeDimWOatkABQJEOMHy9BRPdF3YS2F0dw9tHQ35oE74tmDF/eB 8Oo6U3sUS08tyv++q4guFQw22vhSukZb5nxv1B4mfrhllyQIpUip7919wpoOww== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Mon, 12 Feb 2024 14:44:34 +0100 Subject: [PATCH v6 03/13] dt-bindings: clock: mobileye,eyeq5-clk: add bindings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240212-mbly-clk-v6-3-c46fa1f93839@bootlin.com> References: <20240212-mbly-clk-v6-0-c46fa1f93839@bootlin.com> In-Reply-To: <20240212-mbly-clk-v6-0-c46fa1f93839@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= , Krzysztof Kozlowski X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790703398041413886 X-GMAIL-MSGID: 1790703398041413886 Add DT schema bindings for the EyeQ5 clock controller driver. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Théo Lebrun --- .../bindings/clock/mobileye,eyeq5-clk.yaml | 51 ++++++++++++++++++++++ MAINTAINERS | 2 + include/dt-bindings/clock/mobileye,eyeq5-clk.h | 22 ++++++++++ 3 files changed, 75 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/mobileye,eyeq5-clk.yaml b/Documentation/devicetree/bindings/clock/mobileye,eyeq5-clk.yaml new file mode 100644 index 000000000000..2d4f2cde1e58 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mobileye,eyeq5-clk.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mobileye,eyeq5-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mobileye EyeQ5 clock controller + +description: + The EyeQ5 clock controller handles 10 read-only PLLs derived from the main + crystal clock. It also exposes one divider clock, a child of one of the PLLs. + Its registers live in a shared region called OLB. + +maintainers: + - Grégory Clement + - Théo Lebrun + - Vladimir Kondratiev + +properties: + compatible: + const: mobileye,eyeq5-clk + + reg: + maxItems: 2 + + reg-names: + items: + - const: plls + - const: ospi + + "#clock-cells": + const: 1 + + clocks: + maxItems: 1 + description: + Input parent clock to all PLLs. Expected to be the main crystal. + + clock-names: + items: + - const: ref + +required: + - compatible + - reg + - reg-names + - "#clock-cells" + - clocks + - clock-names + +additionalProperties: false diff --git a/MAINTAINERS b/MAINTAINERS index bc5e34d1eaaf..bd21d03e1771 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14788,10 +14788,12 @@ M: Gregory CLEMENT M: Théo Lebrun L: linux-mips@vger.kernel.org S: Maintained +F: Documentation/devicetree/bindings/clock/mobileye,eyeq5-clk.yaml F: Documentation/devicetree/bindings/mips/mobileye.yaml F: arch/mips/boot/dts/mobileye/ F: arch/mips/configs/eyeq5_defconfig F: arch/mips/mobileye/board-epm5.its.S +F: include/dt-bindings/clock/mobileye,eyeq5-clk.h F: include/dt-bindings/soc/mobileye,eyeq5.h MODULE SUPPORT diff --git a/include/dt-bindings/clock/mobileye,eyeq5-clk.h b/include/dt-bindings/clock/mobileye,eyeq5-clk.h new file mode 100644 index 000000000000..26d8930335e4 --- /dev/null +++ b/include/dt-bindings/clock/mobileye,eyeq5-clk.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2024 Mobileye Vision Technologies Ltd. + */ + +#ifndef _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H +#define _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H + +#define EQ5C_PLL_CPU 0 +#define EQ5C_PLL_VMP 1 +#define EQ5C_PLL_PMA 2 +#define EQ5C_PLL_VDI 3 +#define EQ5C_PLL_DDR0 4 +#define EQ5C_PLL_PCI 5 +#define EQ5C_PLL_PER 6 +#define EQ5C_PLL_PMAC 7 +#define EQ5C_PLL_MPC 8 +#define EQ5C_PLL_DDR1 9 + +#define EQ5C_DIV_OSPI 10 + +#endif