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[31.11.218.106]) by smtp.gmail.com with ESMTPSA id rf19-20020a1709076a1300b00a3743142429sm108255ejc.39.2024.02.08.13.59.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 13:59:35 -0800 (PST) From: =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= To: Russell King , Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Matthias Brugger , AngeloGioacchino Del Regno , devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= Subject: [PATCH V2 1/3] dt-bindings: arm: mediatek: convert hifsys to the json-schema clock Date: Thu, 8 Feb 2024 22:59:24 +0100 Message-Id: <20240208215926.10085-2-zajec5@gmail.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20240208215926.10085-1-zajec5@gmail.com> References: <20240208215926.10085-1-zajec5@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790369859341694901 X-GMAIL-MSGID: 1790369859341694901 From: Rafał Miłecki This helps validating DTS files. Introduced changes: 1. Documented "reg" property 2. Documented "#reset-cells" property 3. Dropped "syscon" as it was incorrectly used 4. Adjusted "compatible" and "reg" in example Signed-off-by: Rafał Miłecki Reviewed-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno --- .../bindings/arm/mediatek/mediatek,hifsys.txt | 26 ---------- .../clock/mediatek,mt2701-hifsys.yaml | 51 +++++++++++++++++++ 2 files changed, 51 insertions(+), 26 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt2701-hifsys.yaml diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt deleted file mode 100644 index 323905af82c3..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt +++ /dev/null @@ -1,26 +0,0 @@ -Mediatek hifsys controller -============================ - -The Mediatek hifsys controller provides various clocks and reset -outputs to the system. - -Required Properties: - -- compatible: Should be: - - "mediatek,mt2701-hifsys", "syscon" - - "mediatek,mt7622-hifsys", "syscon" - - "mediatek,mt7623-hifsys", "mediatek,mt2701-hifsys", "syscon" -- #clock-cells: Must be 1 - -The hifsys controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -hifsys: clock-controller@1a000000 { - compatible = "mediatek,mt2701-hifsys", "syscon"; - reg = <0 0x1a000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt2701-hifsys.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt2701-hifsys.yaml new file mode 100644 index 000000000000..eb429337cdf4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt2701-hifsys.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt2701-hifsys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek hifsys controller + +description: + The Mediatek hifsys controller provides various clocks and reset outputs to + the system. + +maintainers: + - Matthias Brugger + +properties: + compatible: + oneOf: + - items: + - enum: + - mediatek,mt2701-hifsys + - mediatek,mt7622-hifsys + - items: + - enum: + - mediatek,mt7623-hifsys + - const: mediatek,mt2701-hifsys + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + description: The available clocks are defined in dt-bindings/clock/mt*-clk.h + + "#reset-cells": + const: 1 + +required: + - reg + - "#clock-cells" + +additionalProperties: false + +examples: + - | + clock-controller@1a000000 { + compatible = "mediatek,mt2701-hifsys"; + reg = <0x1a000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + };