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bh=gp0Jc6yWvRgb0ZO7bBbrnkeUPabEgmu355DVGo33jtM=; b=Dbg6R4PWkO1rd+HkAynLWhW/UbG7OYlF571/VBCkjZd9hnDFxHDP7Ts/ tiAdZw7Kx5b/ysNkBzpHz5/RG+Te7B3vJ23LAXyQY+aMgOBeUIJfgykDh 3DcfItG7wi9nwQzUnx4u8ViMNt9IInt3ia7ubsABVAqtAxSBfJOf2UyAF c7tRxkpEAGoyPBvND2dwl0tF5zpLXYkIVxpypvmr9CyzFvWSrqd7t0hEi rXhXwyiRGbR56IMEoQf4PSKFLoepyHZMdwcFMe+CKHUTdq9mEhzCoTYl3 zeRvON9VaSvev4MdRWVGkPSqJNkvreQRvZN6FlmptBCvW9sjYbGlztjie w==; X-IronPort-AV: E=McAfee;i="6600,9927,10977"; a="1341362" X-IronPort-AV: E=Sophos;i="6.05,253,1701158400"; d="scan'208";a="1341362" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2024 04:10:36 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.05,253,1701158400"; d="scan'208";a="1625964" Received: from ijarvine-desk1.ger.corp.intel.com (HELO localhost) ([10.246.52.95]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2024 04:10:33 -0800 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: Thomas Bogendoerfer , linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, Sergio Paracuellos Cc: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Subject: [PATCH v2 4/4] MIPS: TXx9: Use PCI_SET_ERROR_RESPONSE() Date: Thu, 8 Feb 2024 14:09:59 +0200 Message-Id: <20240208120959.2513-5-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240208120959.2513-1-ilpo.jarvinen@linux.intel.com> References: <20240208120959.2513-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790337210569388938 X-GMAIL-MSGID: 1790337210569388938 Instead of literal, PCI error value should be set with PCI_SET_ERROR_RESPONSE(). Use it in tx4927_pci_config_read(). Signed-off-by: Ilpo Järvinen --- arch/mips/pci/ops-tx4927.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/pci/ops-tx4927.c b/arch/mips/pci/ops-tx4927.c index 670efbc5c585..37087f4137ee 100644 --- a/arch/mips/pci/ops-tx4927.c +++ b/arch/mips/pci/ops-tx4927.c @@ -144,7 +144,7 @@ static int tx4927_pci_config_read(struct pci_bus *bus, unsigned int devfn, ret = mkaddr(bus, devfn, where, pcicptr); if (ret != PCIBIOS_SUCCESSFUL) { - *val = 0xffffffff; + PCI_SET_ERROR_RESPONSE(val); return ret; } switch (size) {