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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id l14-20020a05600c4f0e00b0040ec8330c8asm4983260wmq.39.2024.02.07.03.15.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Feb 2024 03:15:21 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, semen.protsenko@linaro.org Cc: krzysztof.kozlowski@linaro.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, robh+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, Tudor Ambarus Subject: [PATCH v2 4/4] spi: s3c64xx: add support for google,gs101-spi Date: Wed, 7 Feb 2024 11:15:16 +0000 Message-ID: <20240207111516.2563218-5-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240207111516.2563218-1-tudor.ambarus@linaro.org> References: <20240207111516.2563218-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790139025572308570 X-GMAIL-MSGID: 1790238686807761808 Add support for GS101 SPI. GS101 integrates 16 SPI nodes, all with 64 bytes FIFOs. GS101 allows just 32 bit register accesses, otherwise a Serror Interrupt is raised. Do the write reg accesses in 32 bits. Reviewed-by: Sam Protsenko Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 014fcc933c90..7ab3f3c2e9aa 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -17,7 +17,7 @@ #include -#define MAX_SPI_PORTS 12 +#define MAX_SPI_PORTS 16 #define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1) #define AUTOSUSPEND_TIMEOUT 2000 @@ -1534,6 +1534,19 @@ static const struct s3c64xx_spi_port_config fsd_spi_port_config = { .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, }; +static const struct s3c64xx_spi_port_config gs101_spi_port_config = { + .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, + .rx_lvl_offset = 15, + .tx_st_done = 25, + .clk_div = 4, + .high_speed = true, + .clk_from_cmu = true, + .has_loopback = true, + .use_32bit_io = true, + .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, +}; + static const struct platform_device_id s3c64xx_spi_driver_ids[] = { { .name = "s3c2443-spi", @@ -1546,6 +1559,9 @@ static const struct platform_device_id s3c64xx_spi_driver_ids[] = { }; static const struct of_device_id s3c64xx_spi_dt_match[] = { + { .compatible = "google,gs101-spi", + .data = &gs101_spi_port_config, + }, { .compatible = "samsung,s3c2443-spi", .data = (void *)&s3c2443_spi_port_config, },