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[139.178.88.99]) by mx.google.com with ESMTPS id bw13-20020a056a02048d00b005d8b7053276si1228997pgb.160.2024.02.07.01.46.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Feb 2024 01:46:06 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-56241-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) client-ip=139.178.88.99; Authentication-Results: mx.google.com; arc=pass (i=1 spf=pass spfdomain=huawei.com dmarc=pass fromdomain=huawei.com); spf=pass (google.com: domain of linux-kernel+bounces-56241-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-56241-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=fail (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=huawei.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id D44C428310F for ; Wed, 7 Feb 2024 09:43:52 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1312023748; Wed, 7 Feb 2024 09:43:42 +0000 (UTC) Received: from szxga05-in.huawei.com (szxga05-in.huawei.com [45.249.212.191]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9187220DCF for ; Wed, 7 Feb 2024 09:43:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.191 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707299020; cv=none; b=seX/HCwTS2qIDYNch1MGzCIqgdlB1sBg1fKL4ezJIiG+5qUEIdiCog1EHEztHGulvU42F8LAnwxKoZVWaB3OFmyQIx1OHyD3igiMTjFuhr7QdYVcpNy8CmmHT4Thb6ZjyWk0oFRHXI/K+j9XkZxWV/Nnk7E1grtYPUYs0dJJK/g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707299020; c=relaxed/simple; bh=Bd2Uen+kEEv0rDyXp6hDQY1ojZRMOd7eK03W3Z2GJPw=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=GZX0VXeYG3ftwPODP2ASWGnZhGG+mQuSWBQo1e5ZBLnCvA6kHrDqDeZDWaGQcwF5nc8AVWiMtYx7Y2GPeHWSoieUWzdEMN6hq7n8zSPuIIdpIQ9UhSg+KVg36wLPcrJcP/3DrgYf83smFAxi0bShYMhlDdIa3mnpSProB2IdFqc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.191 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.88.234]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4TVFW62Vw1z1gycc; Wed, 7 Feb 2024 17:41:38 +0800 (CST) Received: from dggpeml500002.china.huawei.com (unknown [7.185.36.158]) by mail.maildlp.com (Postfix) with ESMTPS id B6AC91400CF; Wed, 7 Feb 2024 17:43:34 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by dggpeml500002.china.huawei.com (7.185.36.158) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 7 Feb 2024 17:43:34 +0800 From: Junhao He To: , , CC: , , , , Subject: [PATCH] drivers/perf: hisi: Enable HiSilicon Erratum 162700402 quirk for UC PMU Date: Wed, 7 Feb 2024 17:42:45 +0800 Message-ID: <20240207094245.34195-1-hejunhao3@huawei.com> X-Mailer: git-send-email 2.33.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To dggpeml500002.china.huawei.com (7.185.36.158) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790232930882306733 X-GMAIL-MSGID: 1790232930882306733 HiSilicon UC PMU v2 suffers the erratum 162700402 that the PMU counter cannot be set due to the lack of clock under power saving mode. This will lead to error or inaccurate counts. The clock can be enabled by the PMU global enabling control. This patch tries to fix this by set the UC PMU enable before set event period to turn on the clock, and then restore the UC PMU configuration. The counter register can hold its value without a clock. Signed-off-by: Junhao He --- drivers/perf/hisilicon/hisi_uncore_uc_pmu.c | 40 ++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/drivers/perf/hisilicon/hisi_uncore_uc_pmu.c b/drivers/perf/hisilicon/hisi_uncore_uc_pmu.c index 636fb79647c8..8e7a9e1f419a 100644 --- a/drivers/perf/hisilicon/hisi_uncore_uc_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_uc_pmu.c @@ -287,10 +287,48 @@ static u64 hisi_uc_pmu_read_counter(struct hisi_pmu *uc_pmu, return readq(uc_pmu->base + HISI_UC_CNTR_REGn(hwc->idx)); } -static void hisi_uc_pmu_write_counter(struct hisi_pmu *uc_pmu, +static bool hisi_uc_pmu_get_glb_en_state(struct hisi_pmu *uc_pmu) +{ + u32 val; + + val = readl(uc_pmu->base + HISI_UC_EVENT_CTRL_REG); + return !!FIELD_GET(HISI_UC_EVENT_GLB_EN, val); +} + +static void hisi_uc_pmu_write_counter_quirk_hip09(struct hisi_pmu *uc_pmu, struct hw_perf_event *hwc, u64 val) { + bool enable = hisi_uc_pmu_get_glb_en_state(uc_pmu); + + /* Set the UC PMU enable to turn on the clock. */ + if (!enable) + hisi_uc_pmu_start_counters(uc_pmu); + writeq(val, uc_pmu->base + HISI_UC_CNTR_REGn(hwc->idx)); + + /* + * The counter register can hold its value without a clock. We need + * restore the UC PMU configuration. The irq handler will also call + * the function to set period. At this time, PMU is still enabled and + * we cannot directly disable the PMU. + */ + if (!enable) + hisi_uc_pmu_stop_counters(uc_pmu); +} + +static void hisi_uc_pmu_write_counter(struct hisi_pmu *uc_pmu, + struct hw_perf_event *hwc, u64 val) +{ + /* + * HiSilicon UC PMU v2 suffers the erratum 162700402 that the PMU + * counter cannot be set due to the lack of clock under power saving + * mode. This will lead to error or inaccurate counts. The clock can + * be enabled by the PMU global enabling control. + */ + if (uc_pmu->identifier == HISI_PMU_V2) + hisi_uc_pmu_write_counter_quirk_hip09(uc_pmu, hwc, val); + else + writeq(val, uc_pmu->base + HISI_UC_CNTR_REGn(hwc->idx)); } static void hisi_uc_pmu_enable_counter_int(struct hisi_pmu *uc_pmu,