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Mon, 5 Feb 2024 15:01:33 -0800 From: To: , , , , , , , , , , , , , CC: , , , , , , , , , , , , , Subject: [PATCH v17 1/3] vfio/pci: rename and export do_io_rw() Date: Tue, 6 Feb 2024 04:31:21 +0530 Message-ID: <20240205230123.18981-2-ankita@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240205230123.18981-1-ankita@nvidia.com> References: <20240205230123.18981-1-ankita@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099D3:EE_|PH8PR12MB7232:EE_ X-MS-Office365-Filtering-Correlation-Id: 49281476-ea14-4b1f-5eb6-08dc269e705b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: uP6EQhDBcYIq92FhaMayqiPHcxqvvvuXNP32RAfUfKdXqFRGD1yBFYl28YiVcFhn66ookEtPVS/dExo5Vbbj1RFJx3Tucz6E7JFmTDNonzBjLyZwQ+Nt6DXqow2uQdMdTMep0d5Ze3/6jA2NkNwTQeN+2Oz86adaUfifUqpWjfvJZWHZXy/te1CNbXUPfRN6e/4THfF1U5eQhTCfNyBQuBPtRf68JsXThgotn2EInuB131pTitJ0CHynXeb+gHyn8QV7DvEw3V6PQCAe6mvcZeFAO2Galtws/gLXYKBRpVNrFuDajg4FdKb7JiFN0PJWW8oPyoF4HqhUE2VvInQUrE1qkrGC0eSUZAejvir7CpItXBhhPuHidU7k554V+VKzY7e7YgGsNa/w24CBnvt8zXQ8lVc7uwsbpvW9AAjjQjzhQO8fDWjoMYUREWpuQQx+etwe/UnHgk0CbazG/8VDPmzNjGSW86RgqpvXxKNDjkKNwvEOWUj5vbWxPv+8hmM4XxLhBjuljZmcGEJejoA4sS1cM6gQHsKT3DGBU/HPvRmIFKJj0RoMBXiWPUN/nPsA+W40+Cr/C17/dsHQOd9mqkY4BeperDwUR5RNVUAVfPC+q46QDj9kgkQGMOoenn7uXR3uixY3GMHz3M+4SARPYiHQC6a5ysWb8dUinuoz0sLGAVVLDEW5eVMtBXZbbOv+zYD8WQwHbMCS5CcPDfswIQ+jXtcyU3Gp3oOPI5u0ow8DhmMZaSu4o2WamHDqtj/A X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(346002)(396003)(39860400002)(136003)(376002)(230922051799003)(82310400011)(64100799003)(186009)(1800799012)(451199024)(40470700004)(36840700001)(46966006)(7636003)(110136005)(316002)(54906003)(6636002)(83380400001)(82740400003)(356005)(2616005)(7696005)(6666004)(1076003)(26005)(2906002)(7416002)(70206006)(70586007)(86362001)(5660300002)(478600001)(8676002)(336012)(47076005)(4326008)(426003)(8936002)(36756003)(40480700001)(40460700003)(2876002)(36860700001)(921011)(41300700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Feb 2024 23:01:51.0086 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 49281476-ea14-4b1f-5eb6-08dc269e705b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D3.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7232 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790101928967393862 X-GMAIL-MSGID: 1790101928967393862 From: Ankit Agrawal do_io_rw() is used to read/write to the device MMIO. The grace hopper VFIO PCI variant driver require this functionality to read/write to its memory. Rename this as vfio_pci_core functions and export as GPL. Signed-off-by: Ankit Agrawal Reviewed-by: Kevin Tian --- drivers/vfio/pci/vfio_pci_rdwr.c | 16 +++++++++------- include/linux/vfio_pci_core.h | 5 ++++- 2 files changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/vfio/pci/vfio_pci_rdwr.c b/drivers/vfio/pci/vfio_pci_rdwr.c index 07fea08ea8a2..03b8f7ada1ac 100644 --- a/drivers/vfio/pci/vfio_pci_rdwr.c +++ b/drivers/vfio/pci/vfio_pci_rdwr.c @@ -96,10 +96,10 @@ VFIO_IOREAD(32) * reads with -1. This is intended for handling MSI-X vector tables and * leftover space for ROM BARs. */ -static ssize_t do_io_rw(struct vfio_pci_core_device *vdev, bool test_mem, - void __iomem *io, char __user *buf, - loff_t off, size_t count, size_t x_start, - size_t x_end, bool iswrite) +ssize_t vfio_pci_core_do_io_rw(struct vfio_pci_core_device *vdev, bool test_mem, + void __iomem *io, char __user *buf, + loff_t off, size_t count, size_t x_start, + size_t x_end, bool iswrite) { ssize_t done = 0; int ret; @@ -201,6 +201,7 @@ static ssize_t do_io_rw(struct vfio_pci_core_device *vdev, bool test_mem, return done; } +EXPORT_SYMBOL_GPL(vfio_pci_core_do_io_rw); int vfio_pci_core_setup_barmap(struct vfio_pci_core_device *vdev, int bar) { @@ -279,8 +280,8 @@ ssize_t vfio_pci_bar_rw(struct vfio_pci_core_device *vdev, char __user *buf, x_end = vdev->msix_offset + vdev->msix_size; } - done = do_io_rw(vdev, res->flags & IORESOURCE_MEM, io, buf, pos, - count, x_start, x_end, iswrite); + done = vfio_pci_core_do_io_rw(vdev, res->flags & IORESOURCE_MEM, io, buf, pos, + count, x_start, x_end, iswrite); if (done >= 0) *ppos += done; @@ -348,7 +349,8 @@ ssize_t vfio_pci_vga_rw(struct vfio_pci_core_device *vdev, char __user *buf, * probing, so we don't currently worry about access in relation * to the memory enable bit in the command register. */ - done = do_io_rw(vdev, false, iomem, buf, off, count, 0, 0, iswrite); + done = vfio_pci_core_do_io_rw(vdev, false, iomem, buf, off, count, + 0, 0, iswrite); vga_put(vdev->pdev, rsrc); diff --git a/include/linux/vfio_pci_core.h b/include/linux/vfio_pci_core.h index 85e84b92751b..cf9480a31f3e 100644 --- a/include/linux/vfio_pci_core.h +++ b/include/linux/vfio_pci_core.h @@ -130,7 +130,10 @@ void vfio_pci_core_finish_enable(struct vfio_pci_core_device *vdev); int vfio_pci_core_setup_barmap(struct vfio_pci_core_device *vdev, int bar); pci_ers_result_t vfio_pci_core_aer_err_detected(struct pci_dev *pdev, pci_channel_state_t state); - +ssize_t vfio_pci_core_do_io_rw(struct vfio_pci_core_device *vdev, bool test_mem, + void __iomem *io, char __user *buf, + loff_t off, size_t count, size_t x_start, + size_t x_end, bool iswrite); #define VFIO_IOWRITE_DECLATION(size) \ int vfio_pci_core_iowrite##size(struct vfio_pci_core_device *vdev, \ bool test_mem, u##size val, void __iomem *io);