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b=pT2iCW1HT+oV4+fuiaYLwPkkdghWTxGCefG++q5gt9eBBYfDwAqO6QGahvP9ZpicbRKFrJxQ4U+4LCeVFsUzmVNkRwOJWV1lNXDpaQBhGxXwDwEfD/yHvWLj79RVXE8NBGjSBiYXn0imxBEobjlx0hXqaMb+fKIDl36n7rBTAQc= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) by AS8PR04MB7733.eurprd04.prod.outlook.com (2603:10a6:20b:288::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7249.34; Mon, 5 Feb 2024 17:34:19 +0000 Received: from PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::c8b4:5648:8948:e85c]) by PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::c8b4:5648:8948:e85c%3]) with mapi id 15.20.7249.032; Mon, 5 Feb 2024 17:34:19 +0000 From: Frank Li To: lpieralisi@kernel.org Cc: Frank.li@nxp.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, krzysztof.kozlowski@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v10 05/14] PCI: imx6: Simplify configure_type() by using mode_off and mode_mask Date: Mon, 5 Feb 2024 12:33:26 -0500 Message-Id: <20240205173335.1120469-6-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240205173335.1120469-1-Frank.Li@nxp.com> References: <20240205173335.1120469-1-Frank.Li@nxp.com> X-ClientProxiedBy: BYAPR07CA0041.namprd07.prod.outlook.com (2603:10b6:a03:60::18) To PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PAXPR04MB9642:EE_|AS8PR04MB7733:EE_ X-MS-Office365-Filtering-Correlation-Id: 08f8aa86-cb50-4070-a4f0-08dc2670af23 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Reviewed-by: Manivannan Sadhasivam Signed-off-by: Frank Li --- Notes: Chagne from v8 to v9 - add Manivannan's review tag Change from v7 to v8 - replace simple with simplify - remove reduntant comments about FILED_PREP Change from v3 to v7 - none Change from v2 to v3 - none Change from v1 to v2 - use ffs() to fixe build error. Change from v2 to v3 - none Change from v1 to v2 - use ffs() to fixe build error. drivers/pci/controller/dwc/pci-imx6.c | 59 ++++++++++++++++++--------- 1 file changed, 39 insertions(+), 20 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 8c816ff159115..4eeaf54709afd 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -68,6 +68,7 @@ enum imx6_pcie_variants { #define IMX6_PCIE_MAX_CLKS 6 +#define IMX6_PCIE_MAX_INSTANCES 2 struct imx6_pcie_drvdata { enum imx6_pcie_variants variant; enum dw_pcie_device_mode mode; @@ -78,6 +79,8 @@ struct imx6_pcie_drvdata { const u32 clks_cnt; const u32 ltssm_off; const u32 ltssm_mask; + const u32 mode_off[IMX6_PCIE_MAX_INSTANCES]; + const u32 mode_mask[IMX6_PCIE_MAX_INSTANCES]; }; struct imx6_pcie { @@ -174,32 +177,24 @@ static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie) static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie) { - unsigned int mask, val, mode; + const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; + unsigned int mask, val, mode, id; - if (imx6_pcie->drvdata->mode == DW_PCIE_EP_TYPE) + if (drvdata->mode == DW_PCIE_EP_TYPE) mode = PCI_EXP_TYPE_ENDPOINT; else mode = PCI_EXP_TYPE_ROOT_PORT; - switch (imx6_pcie->drvdata->variant) { - case IMX8MQ: - case IMX8MQ_EP: - if (imx6_pcie->controller_id == 1) { - mask = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE; - val = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, - mode); - } else { - mask = IMX6Q_GPR12_DEVICE_TYPE; - val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, mode); - } - break; - default: - mask = IMX6Q_GPR12_DEVICE_TYPE; - val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, mode); - break; - } + id = imx6_pcie->controller_id; + + /* If mode_mask[id] is zero, means each controller have its individual gpr */ + if (!drvdata->mode_mask[id]) + id = 0; + + mask = drvdata->mode_mask[id]; + val = mode << (ffs(mask) - 1); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val); + regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->mode_off[id], mask, val); } static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val) @@ -1383,6 +1378,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { .clks_cnt = ARRAY_SIZE(imx6q_clks), .ltssm_off = IOMUXC_GPR12, .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, [IMX6SX] = { .variant = IMX6SX, @@ -1394,6 +1391,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { .clks_cnt = ARRAY_SIZE(imx6sx_clks), .ltssm_off = IOMUXC_GPR12, .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, [IMX6QP] = { .variant = IMX6QP, @@ -1406,6 +1405,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { .clks_cnt = ARRAY_SIZE(imx6q_clks), .ltssm_off = IOMUXC_GPR12, .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, [IMX7D] = { .variant = IMX7D, @@ -1415,6 +1416,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { .gpr = "fsl,imx7d-iomuxc-gpr", .clk_names = imx6q_clks, .clks_cnt = ARRAY_SIZE(imx6q_clks), + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, [IMX8MQ] = { .variant = IMX8MQ, @@ -1423,6 +1426,10 @@ static const struct imx6_pcie_drvdata drvdata[] = { .gpr = "fsl,imx8mq-iomuxc-gpr", .clk_names = imx8mq_clks, .clks_cnt = ARRAY_SIZE(imx8mq_clks), + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .mode_off[1] = IOMUXC_GPR12, + .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, }, [IMX8MM] = { .variant = IMX8MM, @@ -1432,6 +1439,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { .gpr = "fsl,imx8mm-iomuxc-gpr", .clk_names = imx8mm_clks, .clks_cnt = ARRAY_SIZE(imx8mm_clks), + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, [IMX8MP] = { .variant = IMX8MP, @@ -1441,6 +1450,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { .gpr = "fsl,imx8mp-iomuxc-gpr", .clk_names = imx8mm_clks, .clks_cnt = ARRAY_SIZE(imx8mm_clks), + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, [IMX8MQ_EP] = { .variant = IMX8MQ_EP, @@ -1450,6 +1461,10 @@ static const struct imx6_pcie_drvdata drvdata[] = { .gpr = "fsl,imx8mq-iomuxc-gpr", .clk_names = imx8mq_clks, .clks_cnt = ARRAY_SIZE(imx8mq_clks), + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .mode_off[1] = IOMUXC_GPR12, + .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, }, [IMX8MM_EP] = { .variant = IMX8MM_EP, @@ -1458,6 +1473,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { .gpr = "fsl,imx8mm-iomuxc-gpr", .clk_names = imx8mm_clks, .clks_cnt = ARRAY_SIZE(imx8mm_clks), + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, [IMX8MP_EP] = { .variant = IMX8MP_EP, @@ -1466,6 +1483,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { .gpr = "fsl,imx8mp-iomuxc-gpr", .clk_names = imx8mm_clks, .clks_cnt = ARRAY_SIZE(imx8mm_clks), + .mode_off[0] = IOMUXC_GPR12, + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, }, };