From patchwork Mon Feb 5 07:19:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pawan Gupta X-Patchwork-Id: 196808 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp847659dyb; Mon, 5 Feb 2024 04:45:12 -0800 (PST) X-Google-Smtp-Source: AGHT+IFKVqAuFKj9x+TPRFPbatZ3E3kv6jWIV0Hn0SjqWtA+pJ37Gxwn4MDOPwEfbxAKYgdLNcib X-Received: by 2002:a05:6122:4c83:b0:4c0:1cb7:1ba9 with SMTP id fg3-20020a0561224c8300b004c01cb71ba9mr2769083vkb.9.1707137112373; Mon, 05 Feb 2024 04:45:12 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707137112; cv=pass; d=google.com; s=arc-20160816; b=m2S8sc2vbl6yD6MNOBlTiDN1Sr5bJNoRfAqn27bUrf3aavjFl/4e8p4dNOqvkGKL+l D4Z7ZvQadPvYQRaJGENKF8Wla6r6DQQGOaM1bLdqzn98v/yN8cFcavmnk6DyeOtuzrpW D+VkpSOrcz89HW52k+J4XEb0uw9eg4BJT16YLeOVde6iXc97JTkVKmLbliFkjjzPUefK 5LefoNCKcsa6bGAw+w/xaHEfTKUbbWcQdBV6fg7URkg6glz3hRyh/6p/4s0s4XWf4RNk WeAMaPSCRySzDNabLOSLZLJ/JbJ3HSltBYfF8yZ/mmZojxUQ36U73nbkYZVGmsi7xAWK tKAQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=in-reply-to:content-disposition:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:message-id:subject:cc :to:from:date:dkim-signature; bh=h6Av1fjqQhua5cardZuvjbd2yKTW8u/OaTgaLYxrjTs=; fh=x96da3Oq9LRLcqWY7RXb7/K6ncmkP1RnzKfia1N85yU=; b=UTAPvRP37qwdOHr0s+afjR8pZ9AX4t3GdcqMvzuQIJSKqF8qi3e9XL6XBUa15BnMKi RSP3lNjRTC1CHZ3M5p/RLMCUF/CfAMbPzS62fz9CBsnVGgKVjUbACGtZ3slh4JCdYkTY yHRjIh6AMV3BYcIt6R/94DaYW6j9MNoQjM9byhpyESyhur2egWAxv5niOeFq0ZsprSke N94rUr8Lpq63YJv3RYT+oAizZFVkgjlCa5pur3HZV3jqwY1vFHG4gaPVwCnIrZWep+PM 0H35hpnC9JmVJJy6EIELYMLdwwksohoCll6p0RHAUicGAy+OiHaZUf2wWNiIfwigwdMU gNpw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=GrCP8cLI; arc=pass (i=1 dkim=pass dkdomain=intel.com dmarc=pass fromdomain=linux.intel.com); spf=pass (google.com: domain of linux-kernel+bounces-52120-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-52120-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com X-Forwarded-Encrypted: i=1; AJvYcCV9R4kw+RRCDpsbou5DFpjHOR62BqjpGVz5OrGwm+7eYpoSDZCXl9zhLezNJOkQKaUQlcbKJojEEMI5PYDlnMbdqWUkhQ== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. [2604:1380:45d1:ec00::1]) by mx.google.com with ESMTPS id gu6-20020a056214260600b0068c929892f1si6056263qvb.82.2024.02.05.04.45.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Feb 2024 04:45:12 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-52120-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=GrCP8cLI; arc=pass (i=1 dkim=pass dkdomain=intel.com dmarc=pass fromdomain=linux.intel.com); spf=pass (google.com: domain of linux-kernel+bounces-52120-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-52120-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id B1E7B1C2361B for ; Mon, 5 Feb 2024 07:20:25 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 441BA12E4E; Mon, 5 Feb 2024 07:19:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="GrCP8cLI" Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 99A0612B6B; Mon, 5 Feb 2024 07:19:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707117560; cv=none; b=dX1MZNGNm6NnRMUd2ksVg9NuNwnYeCv3jIQ6MtSZ+t5pz0ODQhpjlpe/HoXTubTTvamv/64SQP0lYtveoWVkiz3mHj7zxFtdWw0B4XpV3sQ41ya7Hvo3zOIvEt0UVaoP41aOUpSXPfYH8xj4PYB75h07xk77zIS0qdr5ucGprAU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707117560; c=relaxed/simple; bh=muMVHd/9060DOMcFxg6pmke63ovxAm+uQnsL/4dWals=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=Ju+aYnGRh/lA+yBXR34KyArmZ/Lrta8BMHYmrhBgpr2KtttuMoA9m5UKTn4Eyu74JAMcF5Ugsp4WgltKxBlb4ERvPFW2u5QF8hc3VKAw9ety8Yl3+pGOANNKdOpBht9SjWPrZqQj3DB+dorCIVXqQ1NjVVaD6TbKBdNdI2l80S4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=GrCP8cLI; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1707117559; x=1738653559; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=muMVHd/9060DOMcFxg6pmke63ovxAm+uQnsL/4dWals=; b=GrCP8cLIC1xmCvgFmRbMiDseXj/eXS8PsbmsE65Wv7f7b06aWuFsKVar OsPrVnz1NjctIa14FofTyiX17pxyBVVnXEWqfkemAzYwpapWBCFpbSuFZ xMnZqnDHPD92zGd2k3oU6unZOBxzUclOdlgaRNtjpg5Nj/CbM158zc0E6 dofurZfnyYPJvNcTBx5su+v+wwJ2AUyXcfYH+tiDIKHn3KK55eOocyuN5 zQ1ZH/t3j3kWa7tRh4N/4vpx7FIjPiyQTj96wlIYYodDVrW5uqeyPLkIi wN62jnLiZQIWA2yiylzdfpgqo5J3vIzgg8JluH3fvrnQxPZ/LNBmOE8DD A==; X-IronPort-AV: E=McAfee;i="6600,9927,10974"; a="634537" X-IronPort-AV: E=Sophos;i="6.05,242,1701158400"; d="scan'208";a="634537" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2024 23:19:18 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.05,242,1701158400"; d="scan'208";a="968143" Received: from tdspence-mobl1.amr.corp.intel.com (HELO desk) ([10.251.0.86]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2024 23:19:17 -0800 Date: Sun, 4 Feb 2024 23:19:16 -0800 From: Pawan Gupta To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Peter Zijlstra , Josh Poimboeuf , Andy Lutomirski , Jonathan Corbet , Sean Christopherson , Paolo Bonzini , tony.luck@intel.com, ak@linux.intel.com, tim.c.chen@linux.intel.com, Andrew Cooper , Nikolay Borisov Cc: linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, Alyssa Milburn , Daniel Sneddon , antonio.gomez.iglesias@linux.intel.com, Pawan Gupta , Dave Hansen , stable@kernel.org Subject: [PATCH v7 2/6] x86/entry_64: Add VERW just before userspace transition Message-ID: <20240204-delay-verw-v7-2-59be2d704cb2@linux.intel.com> X-Mailer: b4 0.12.3 References: <20240204-delay-verw-v7-0-59be2d704cb2@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240204-delay-verw-v7-0-59be2d704cb2@linux.intel.com> X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790063004858868958 X-GMAIL-MSGID: 1790063004858868958 Mitigation for MDS is to use VERW instruction to clear any secrets in CPU Buffers. Any memory accesses after VERW execution can still remain in CPU buffers. It is safer to execute VERW late in return to user path to minimize the window in which kernel data can end up in CPU buffers. There are not many kernel secrets to be had after SWITCH_TO_USER_CR3. Add support for deploying VERW mitigation after user register state is restored. This helps minimize the chances of kernel data ending up into CPU buffers after executing VERW. Note that the mitigation at the new location is not yet enabled. Corner case not handled ======================= Interrupts returning to kernel don't clear CPUs buffers since the exit-to-user path is expected to do that anyways. But, there could be a case when an NMI is generated in kernel after the exit-to-user path has cleared the buffers. This case is not handled and NMI returning to kernel don't clear CPU buffers because: 1. It is rare to get an NMI after VERW, but before returning to userspace. 2. For an unprivileged user, there is no known way to make that NMI less rare or target it. 3. It would take a large number of these precisely-timed NMIs to mount an actual attack. There's presumably not enough bandwidth. 4. The NMI in question occurs after a VERW, i.e. when user state is restored and most interesting data is already scrubbed. Whats left is only the data that NMI touches, and that may or may not be of any interest. Suggested-by: Dave Hansen Cc: stable@kernel.org Signed-off-by: Pawan Gupta --- arch/x86/entry/entry_64.S | 11 +++++++++++ arch/x86/entry/entry_64_compat.S | 1 + 2 files changed, 12 insertions(+) diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index c40f89ab1b4c..9bb485977629 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -161,6 +161,7 @@ syscall_return_via_sysret: SYM_INNER_LABEL(entry_SYSRETQ_unsafe_stack, SYM_L_GLOBAL) ANNOTATE_NOENDBR swapgs + CLEAR_CPU_BUFFERS sysretq SYM_INNER_LABEL(entry_SYSRETQ_end, SYM_L_GLOBAL) ANNOTATE_NOENDBR @@ -573,6 +574,7 @@ SYM_INNER_LABEL(swapgs_restore_regs_and_return_to_usermode, SYM_L_GLOBAL) .Lswapgs_and_iret: swapgs + CLEAR_CPU_BUFFERS /* Assert that the IRET frame indicates user mode. */ testb $3, 8(%rsp) jnz .Lnative_iret @@ -723,6 +725,8 @@ native_irq_return_ldt: */ popq %rax /* Restore user RAX */ + CLEAR_CPU_BUFFERS + /* * RSP now points to an ordinary IRET frame, except that the page * is read-only and RSP[31:16] are preloaded with the userspace @@ -1449,6 +1453,12 @@ nmi_restore: std movq $0, 5*8(%rsp) /* clear "NMI executing" */ + /* + * Skip CLEAR_CPU_BUFFERS here, since it only helps in rare cases like + * NMI in kernel after user state is restored. For an unprivileged user + * these conditions are hard to meet. + */ + /* * iretq reads the "iret" frame and exits the NMI stack in a * single instruction. We are returning to kernel mode, so this @@ -1466,6 +1476,7 @@ SYM_CODE_START(entry_SYSCALL32_ignore) UNWIND_HINT_END_OF_STACK ENDBR mov $-ENOSYS, %eax + CLEAR_CPU_BUFFERS sysretl SYM_CODE_END(entry_SYSCALL32_ignore) diff --git a/arch/x86/entry/entry_64_compat.S b/arch/x86/entry/entry_64_compat.S index de94e2e84ecc..eabf48c4d4b4 100644 --- a/arch/x86/entry/entry_64_compat.S +++ b/arch/x86/entry/entry_64_compat.S @@ -270,6 +270,7 @@ SYM_INNER_LABEL(entry_SYSRETL_compat_unsafe_stack, SYM_L_GLOBAL) xorl %r9d, %r9d xorl %r10d, %r10d swapgs + CLEAR_CPU_BUFFERS sysretl SYM_INNER_LABEL(entry_SYSRETL_compat_end, SYM_L_GLOBAL) ANNOTATE_NOENDBR