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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789812778467461717 X-GMAIL-MSGID: 1789812778467461717 Document the PCIe Controllers on the X1E80100 platform. They are similar to the ones found on SM8550, but they don't have SF QTB clock. Reviewed-by: Krzysztof Kozlowski Acked-by: Manivannan Sadhasivam Signed-off-by: Abel Vesa --- .../devicetree/bindings/pci/qcom,pcie.yaml | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index a93ab3b54066..7381e38b7398 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -41,6 +41,7 @@ properties: - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 - qcom,pcie-sm8550 + - qcom,pcie-x1e80100 - items: - enum: - qcom,pcie-sm8650 @@ -227,6 +228,7 @@ allOf: - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 - qcom,pcie-sm8550 + - qcom,pcie-x1e80100 then: properties: reg: @@ -826,6 +828,32 @@ allOf: items: - const: pci # PCIe core reset + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-x1e80100 + then: + properties: + clocks: + maxItems: 7 + clock-names: + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: noc_aggr # Aggre NoC PCIe AXI clock + - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock + resets: + maxItems: 2 + reset-names: + items: + - const: pci # PCIe core reset + - const: link_down # PCIe link down reset + - if: properties: compatible: @@ -884,6 +912,7 @@ allOf: - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 - qcom,pcie-sm8550 + - qcom,pcie-x1e80100 then: oneOf: - properties: