Message ID | 20240202-llvm-msym32-v1-6-52f0631057d6@flygoat.com |
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State | New |
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Fri, 2 Feb 2024 13:22:09 -0500 (EST) From: Jiaxun Yang <jiaxun.yang@flygoat.com> Date: Fri, 02 Feb 2024 18:21:45 +0000 Subject: [PATCH 6/8] MIPS: Limit MIPS_MT_SMP support by ISA reversion Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: <linux-kernel.vger.kernel.org> List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20240202-llvm-msym32-v1-6-52f0631057d6@flygoat.com> References: <20240202-llvm-msym32-v1-0-52f0631057d6@flygoat.com> In-Reply-To: <20240202-llvm-msym32-v1-0-52f0631057d6@flygoat.com> To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>, Nathan Chancellor <nathan@kernel.org>, Nick Desaulniers <ndesaulniers@google.com>, Bill Wendling <morbo@google.com>, Justin Stitt <justinstitt@google.com> Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Jiaxun Yang <jiaxun.yang@flygoat.com>, Guenter Roeck <linux@roeck-us.net> X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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Series |
MIPS: Aggregate build fixes
|
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Commit Message
Jiaxun Yang
Feb. 2, 2024, 6:21 p.m. UTC
MIPS MT ASE is only available on ISA between Release 1 and Release 5.
Add ISA level dependency to Kconfig to fix build.
Reported-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
v0: https://lore.kernel.org/all/20230414080701.15503-8-jiaxun.yang@flygoat.com/
---
arch/mips/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 797ae590ebdb..c44358a6d93e 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2171,7 +2171,8 @@ config CPU_R4K_CACHE_TLB config MIPS_MT_SMP bool "MIPS MT SMP support (1 TC on each available VPE)" default y - depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS + depends on TARGET_ISA_REV > 0 && TARGET_ISA_REV < 6 + depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MICROMIPS select CPU_MIPSR2_IRQ_VI select CPU_MIPSR2_IRQ_EI select SYNC_R4K