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(fttx-pool-217.61.148.248.bambit.de [217.61.148.248]) by mxbox1.masterlogin.de (Postfix) with ESMTPSA id 07579406E6; Thu, 1 Feb 2024 18:24:16 +0000 (UTC) From: Frank Wunderlich To: Michael Turquette , Stephen Boyd , Matthias Brugger , AngeloGioacchino Del Regno , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Frank Wunderlich , Sam Shih , Daniel Golle , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, Conor Dooley Subject: [PATCH v4 1/2] dt-bindings: reset: mediatek: add MT7988 infracfg reset IDs Date: Thu, 1 Feb 2024 19:24:08 +0100 Message-Id: <20240201182409.39878-2-linux@fw-web.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240201182409.39878-1-linux@fw-web.de> References: <20240201182409.39878-1-linux@fw-web.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Mail-ID: f86ec7b2-db69-458e-813c-2cef7dd7b5cc X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789724223991944066 X-GMAIL-MSGID: 1789724223991944066 From: Frank Wunderlich Add reset constants for using as index in driver and dts. Value is starting again from 0 because resets are used in another device than existing constants. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Acked-by: Conor Dooley --- v4: - add info about restarting ids from 0 to commit message v3: - add pcie reset id as suggested by angelo v2: - add missing commit message and SoB - change value of infrareset to 0 --- include/dt-bindings/reset/mediatek,mt7988-resets.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/dt-bindings/reset/mediatek,mt7988-resets.h b/include/dt-bindings/reset/mediatek,mt7988-resets.h index 493301971367..0eb152889a89 100644 --- a/include/dt-bindings/reset/mediatek,mt7988-resets.h +++ b/include/dt-bindings/reset/mediatek,mt7988-resets.h @@ -10,4 +10,10 @@ /* ETHWARP resets */ #define MT7988_ETHWARP_RST_SWITCH 0 +/* INFRA resets */ +#define MT7988_INFRA_RST0_PEXTP_MAC_SWRST 0 +#define MT7988_INFRA_RST1_THERM_CTRL_SWRST 1 + + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7988 */ +