Message ID | 20240201161258.1013664-6-andre.draszik@linaro.org |
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State | New |
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[34.141.189.94]) by smtp.gmail.com with ESMTPSA id hw18-20020a170907a0d200b00a3600d7c2fbsm3449288ejc.176.2024.02.01.08.13.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 08:13:13 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= <andre.draszik@linaro.org> To: peter.griffin@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@android.com, tudor.ambarus@linaro.org, willmcvicker@google.com, semen.protsenko@linaro.org, alim.akhtar@samsung.com, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Andr=C3=A9?= =?utf-8?q?_Draszik?= <andre.draszik@linaro.org> Subject: [PATCH v3 5/7] arm64: dts: exynos: gs101: enable cmu-peric1 clock controller Date: Thu, 1 Feb 2024 16:11:41 +0000 Message-ID: <20240201161258.1013664-6-andre.draszik@linaro.org> X-Mailer: git-send-email 2.43.0.594.gd9cf4e227d-goog In-Reply-To: <20240201161258.1013664-1-andre.draszik@linaro.org> References: <20240201161258.1013664-1-andre.draszik@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: <linux-kernel.vger.kernel.org> List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789713885760051830 X-GMAIL-MSGID: 1789713885760051830 |
Series |
gs101 oriole: peripheral block 1 (peric1) and i2c12 support
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Commit Message
André Draszik
Feb. 1, 2024, 4:11 p.m. UTC
Enable the cmu-peric1 clock controller. It feeds additional USI, I3C and PWM interfaces / busses. Note that &sysreg_peric1 needs a clock to be able to access its registers and now that Linux knows about this clock, we need to add it in this commit as well so as to keep &sysreg_peric1 working, so that the clock can be enabled as and when needed. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> --- v3: collect Reviewed-by: tags v2: * merge patch #8 from original series version 1 into this patch, i.e. add the clock to &sysreg_peric1 in this commit & update commit message * collect Reviewed-by: tags --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+)
Comments
On Thu, 01 Feb 2024 16:11:41 +0000, André Draszik wrote: > Enable the cmu-peric1 clock controller. It feeds additional USI, I3C > and PWM interfaces / busses. > > Note that &sysreg_peric1 needs a clock to be able to access its > registers and now that Linux knows about this clock, we need to add it > in this commit as well so as to keep &sysreg_peric1 working, so that > the clock can be enabled as and when needed. > > [...] Applied, thanks! [5/7] arm64: dts: exynos: gs101: enable cmu-peric1 clock controller https://git.kernel.org/krzk/linux/c/7d66d98b5bf376a999df13c65bbc0aac3cc9de02 Best regards,
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index aaac04df5e65..e1bcf490309a 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -429,9 +429,20 @@ serial_0: serial@10a00000 { }; }; + cmu_peric1: clock-controller@10c00000 { + compatible = "google,gs101-cmu-peric1"; + reg = <0x10c00000 0x4000>; + #clock-cells = <1>; + clocks = <&ext_24_5m>, + <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>, + <&cmu_top CLK_DOUT_CMU_PERIC1_IP>; + clock-names = "oscclk", "bus", "ip"; + }; + sysreg_peric1: syscon@10c20000 { compatible = "google,gs101-peric1-sysreg", "syscon"; reg = <0x10c20000 0x10000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK>; }; pinctrl_peric1: pinctrl@10c40000 {