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Thu, 1 Feb 2024 06:54:54 -0600 Received: from localhost (uda0496377.dhcp.ti.com [10.24.69.150]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 411Cssoa064890; Thu, 1 Feb 2024 06:54:54 -0600 From: Aradhya Bhatia To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Devicetree List , Linux Kernel List , Linux ARM Kernel List , Tomi Valkeinen , Devarsh Thakkar , Jai Luthra , Aradhya Bhatia Subject: [PATCH 1/3] arm64: dts: ti: k3-am62a-main: Add node for Display SubSystem (DSS) Date: Thu, 1 Feb 2024 18:24:50 +0530 Message-ID: <20240201125452.1920623-2-a-bhatia1@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240201125452.1920623-1-a-bhatia1@ti.com> References: <20240201125452.1920623-1-a-bhatia1@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789701366917291560 X-GMAIL-MSGID: 1789701366917291560 Add Display SubSystem (DSS) DT node for the AM62A7 SoC. The DSS supports one each of video pipeline (vid) and video-lite pipeline (vidl1). The video port 1 (vp1) is tied-off in AM62A SoC, but the pipeline remains active. The video port 2 (vp2) outputs the DPI signals. Both the video ports are connected to the pipelines via 2 identical overlay managers (ovr1 and ovr2). Signed-off-by: Aradhya Bhatia --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 25 +++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index f0b8c9ab1459..d3de5ad3eeb2 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -985,4 +985,29 @@ dphy0: phy@30110000 { power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; + + dss: dss@30200000 { + compatible = "ti,am62a7-dss"; + reg = <0x00 0x30200000 0x00 0x1000>, /* common */ + <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ + <0x00 0x30206000 0x00 0x1000>, /* vid */ + <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ + <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ + <0x00 0x3020a000 0x00 0x1000>, /* vp1: Tied OFF in the SoC */ + <0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */ + reg-names = "common", "vidl1", "vid", + "ovr1", "ovr2", "vp1", "vp2"; + power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 186 6>, + <&k3_clks 186 0>, + <&k3_clks 186 2>; + clock-names = "fck", "vp1", "vp2"; + interrupts = ; + status = "disabled"; + + dss_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; };