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Wed, 31 Jan 2024 15:50:44 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40VLoig4062479; Wed, 31 Jan 2024 15:50:44 -0600 From: Judith Mendez To: Ulf Hansson CC: Adrian Hunter , , , Randolph Sapp , Vignesh Raghavendra Subject: [PATCH v1 2/5] mmc: sdhci_am654: Write ITAPDLY for DDR52 timing Date: Wed, 31 Jan 2024 15:50:41 -0600 Message-ID: <20240131215044.3163469-3-jm@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240131215044.3163469-1-jm@ti.com> References: <20240131215044.3163469-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789644580404563539 X-GMAIL-MSGID: 1789644580404563539 For DDR52 timing, DLL is enabled but tuning is not carried out, therefore the ITAPDLY value in PHY CTRL 4 register is not correct. Fix this by writing ITAPDLY after enabling DLL. Fixes: a161c45f2979 ("mmc: sdhci_am654: Enable DLL only for some speed modes") Signed-off-by: Judith Mendez --- drivers/mmc/host/sdhci_am654.c | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c index a3798c9912f6..ff18a274b6f2 100644 --- a/drivers/mmc/host/sdhci_am654.c +++ b/drivers/mmc/host/sdhci_am654.c @@ -170,7 +170,19 @@ struct sdhci_am654_driver_data { #define DLL_CALIB (1 << 4) }; -static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock) +static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654, + u32 itapdly) +{ + /* Set ITAPCHGWIN before writing to ITAPDLY */ + regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, + 0x1 << ITAPCHGWIN_SHIFT); + regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK, + itapdly << ITAPDLYSEL_SHIFT); + regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); +} + +static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock, + unsigned char timing) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); @@ -236,17 +248,8 @@ static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock) dev_err(mmc_dev(host->mmc), "DLL failed to relock\n"); return; } -} -static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654, - u32 itapdly) -{ - /* Set ITAPCHGWIN before writing to ITAPDLY */ - regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, - 1 << ITAPCHGWIN_SHIFT); - regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK, - itapdly << ITAPDLYSEL_SHIFT); - regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); + sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing]); } static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654, @@ -298,7 +301,7 @@ static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) { - sdhci_am654_setup_dll(host, clock); + sdhci_am654_setup_dll(host, clock, timing); sdhci_am654->dll_enable = true; } else { sdhci_am654_setup_delay_chain(sdhci_am654, timing);