From patchwork Wed Jan 31 10:14:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chintan Vankar X-Patchwork-Id: 194679 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2087:b0:106:209c:c626 with SMTP id gs7csp1810934dyb; Wed, 31 Jan 2024 03:08:40 -0800 (PST) X-Google-Smtp-Source: AGHT+IGKflk6DeoqpwprnBOpy7OjiowpkfwCoY8RZG/e3tBcivt1MbypOryZYDgVrdXH1MyTfykA X-Received: by 2002:a17:906:b80b:b0:a35:da9c:ff80 with SMTP id dv11-20020a170906b80b00b00a35da9cff80mr866753ejb.12.1706699320206; Wed, 31 Jan 2024 03:08:40 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706699320; cv=pass; d=google.com; s=arc-20160816; b=nRSIw0VJDTAqE9Dhl6ig+CJ9HquAdbpOVCQyjCKhyXVALPV2SPyD+yb2WWL9GdGxPY xFsOykRcQVXIOaZQagnDGSLviX7vtiR5KZoDVuuKaf7npqI+9Md6CFbqlF5tlD2UB/7c EQxQwflIr4zd58sZHjzYW35eRoppd4yOzsY6RnL/+Ckd2ib5UsxVpm+I5l0bmKe1GS6o r5AaeD7H3I9aYtx+09OpQH1r4AdXYQy6qhD2ob1gUX++z+J00mz650WmX0S2U5GHeFnK 0k5vB82gBFhsZgtwCFXf0a8ovnW1YLfl0u5ELasDJ5tbRvlLY8Sm1sLiCbBX/JryeeJ2 wCUA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=oqemPubLVRrgYvvfimFAejLxoKvjxzL1JVzVCjpzc9Q=; fh=DFNQGSbswsx9LiBNZ+SHRUiuU7DSEJhQUChK/to2fLg=; b=PromDvUrWqm7qvRyJr4ybKiunUgC58gLJjUUFKcs/BMrpmPfjp1JPeEoW+aT/UFDoe OFMCFYP0kwOiHpdDrMndrpFerLPOaBUsE/2tAqz8qXXkODYc490Ep+w+iMR7eU0ADZNk hvp/IKnLRbnA+kgnUeUlzp2moTX0XTzIjGzFuu4/6XyGrZtj67+HgzPTH2/bnT24EryH L45Bs8VQXW6OxuroSFOg5ljj87DQGTgQ3KRmky/khAUxYeqiBNLf0An1d2HQula7bRCD hV3sltzOMdn3FJivnRAKEraQTHWgaaQ0y8HUDtJ1glLfklquW6LV+d7LRuKKJiRaWPuH Z8Og==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=hfKmreoZ; arc=pass (i=1 spf=pass spfdomain=ti.com dkim=pass dkdomain=ti.com dmarc=pass fromdomain=ti.com); spf=pass (google.com: domain of linux-kernel+bounces-46194-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-46194-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com X-Forwarded-Encrypted: i=1; AJvYcCWCGM2iDi8f9HrxVtHBe6gI6y6aYgOnfyMDQtm3jZvBrI71+/FYUyWC4R5W5DghfNFBtVNmqQtKv4UP9SlLkWu1VA7i+Q== Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. [2604:1380:4601:e00::3]) by mx.google.com with ESMTPS id b9-20020a170906490900b00a3673c19b2esi530866ejq.626.2024.01.31.03.08.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jan 2024 03:08:40 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-46194-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) client-ip=2604:1380:4601:e00::3; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=hfKmreoZ; arc=pass (i=1 spf=pass spfdomain=ti.com dkim=pass dkdomain=ti.com dmarc=pass fromdomain=ti.com); spf=pass (google.com: domain of linux-kernel+bounces-46194-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-46194-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id C5E9E1F2D941 for ; Wed, 31 Jan 2024 10:17:25 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9C84E78683; Wed, 31 Jan 2024 10:15:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="hfKmreoZ" Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2069B76919; Wed, 31 Jan 2024 10:15:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706696126; cv=none; b=eitUx+Q3k4eVtbrX1ku0EqsQ9fhKP4q4/8+Yb9dbCVv6wkPa6K9BdfT07BicBpz3SO4VYofO9pHlL/7gK0CCn3EBRSlkBunQzgf/HhWJn8nqtECHcQkPK+KL2STTPEbWwG9cfkz1PjxSA8gZqwaiW6Y0IsV/ZqlrsXp8xww7tP8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706696126; c=relaxed/simple; bh=DH5NiegzsYQpiijOn8/YrWg0zYL9KB6NJv4gbpeVvEQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Y5FB6bycUiDS8rBQydXrh5XXRyGYGCFaCdyKA5FlgDT1/i2oH68KLYzsDPxhbqfOsXXjvT7ZVtvXFODKCbpWjwnjDMS0AgtVxyhVy0V4Zc7YdpNMLCjHtDx5ZIeYCG5yzdUl0lMGtYVWgWiy3NH4eCnscukBF/WhMEqSEPEs+KY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=hfKmreoZ; arc=none smtp.client-ip=198.47.23.248 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 40VAEpUo065453; Wed, 31 Jan 2024 04:14:51 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1706696091; bh=oqemPubLVRrgYvvfimFAejLxoKvjxzL1JVzVCjpzc9Q=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=hfKmreoZO1hN0nuNHxYFKZbiuQiKZILt9BIdoCUyzB8I9Zjyz4lETxXdka9BjkwYH dAXm89GQGCy0JoI24yf/CjEXoeF+99RfKRZwvSgVMBptuzJj/8e9D0NN1Fb1XGx/AW ykIJh4Xf4l1eiDkbsF8DGQOm2WBOu1qcXUyMlyE0= Received: from DLEE111.ent.ti.com (dlee111.ent.ti.com [157.170.170.22]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 40VAEoXH006848 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 31 Jan 2024 04:14:50 -0600 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 31 Jan 2024 04:14:50 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 31 Jan 2024 04:14:50 -0600 Received: from localhost (chintan-thinkstation-p360-tower.dhcp.ti.com [172.24.227.220]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40VAEnaV110279; Wed, 31 Jan 2024 04:14:50 -0600 From: Chintan Vankar To: Andrew Davis , Peter Rosin , Greg Kroah-Hartman , Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra , Nishanth Menon CC: , , , , , , , Jayesh Choudhary , Chintan Vankar Subject: [PATCH v4 4/6] arm64: dts: ti: k3-j784s4: Add Main CPSW2G node Date: Wed, 31 Jan 2024 15:44:39 +0530 Message-ID: <20240131101441.1362409-5-c-vankar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240131101441.1362409-1-c-vankar@ti.com> References: <20240131101441.1362409-1-c-vankar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789603946435897549 X-GMAIL-MSGID: 1789603946435897549 From: Siddharth Vadapalli Add the device-tree nodes for the Main CPSW2G instance and enable it. Add alias for the Main CPSW2G port to enable Linux to fetch MAC Address for the port directly from U-Boot. Signed-off-by: Siddharth Vadapalli Signed-off-by: Jayesh Choudhary Signed-off-by: Chintan Vankar --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 49 ++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index b74f7d3025de..be028c246c67 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -28,6 +28,7 @@ aliases { i2c0 = &wkup_i2c0; i2c3 = &main_i2c0; ethernet0 = &mcu_cpsw_port1; + ethernet1 = &main_cpsw1_port1; }; memory@80000000 { @@ -280,6 +281,30 @@ &wkup_gpio0 { &main_pmx0 { bootph-all; + main_cpsw2g_default_pins: main-cpsw2g-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0b8, PIN_INPUT, 6) /* (AC34) MCASP1_ACLKX.RGMII1_RD0 */ + J784S4_IOPAD(0x0a0, PIN_INPUT, 6) /* (AD34) MCASP0_AXR12.RGMII1_RD1 */ + J784S4_IOPAD(0x0a4, PIN_INPUT, 6) /* (AJ36) MCASP0_AXR13.RGMII1_RD2 */ + J784S4_IOPAD(0x0a8, PIN_INPUT, 6) /* (AF34) MCASP0_AXR14.RGMII1_RD3 */ + J784S4_IOPAD(0x0b0, PIN_INPUT, 6) /* (AL33) MCASP1_AXR3.RGMII1_RXC */ + J784S4_IOPAD(0x0ac, PIN_INPUT, 6) /* (AE34) MCASP0_AXR15.RGMII1_RX_CTL */ + J784S4_IOPAD(0x08c, PIN_INPUT, 6) /* (AE35) MCASP0_AXR7.RGMII1_TD0 */ + J784S4_IOPAD(0x090, PIN_INPUT, 6) /* (AC35) MCASP0_AXR8.RGMII1_TD1 */ + J784S4_IOPAD(0x094, PIN_INPUT, 6) /* (AG35) MCASP0_AXR9.RGMII1_TD2 */ + J784S4_IOPAD(0x098, PIN_INPUT, 6) /* (AH36) MCASP0_AXR10.RGMII1_TD3 */ + J784S4_IOPAD(0x0b4, PIN_INPUT, 6) /* (AL34) MCASP1_AXR4.RGMII1_TXC */ + J784S4_IOPAD(0x09c, PIN_INPUT, 6) /* (AF35) MCASP0_AXR11.RGMII1_TX_CTL */ + >; + }; + + main_cpsw2g_mdio_default_pins: main-cpsw2g-mdio-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0c0, PIN_INPUT, 6) /* (AD38) MCASP1_AXR0.MDIO0_MDC */ + J784S4_IOPAD(0x0bc, PIN_INPUT, 6) /* (AD33) MCASP1_AFSX.MDIO0_MDIO */ + >; + }; + main_uart8_pins_default: main-uart8-default-pins { bootph-all; pinctrl-single,pins = < @@ -809,6 +834,30 @@ &mcu_cpsw_port1 { phy-handle = <&mcu_phy0>; }; +&main_cpsw1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_cpsw2g_default_pins>; +}; + +&main_cpsw1_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&main_cpsw2g_mdio_default_pins>; + + main_cpsw1_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&main_cpsw1_port1 { + status = "okay"; + phy-mode = "rgmii-rxid"; + phy-handle = <&main_cpsw1_phy0>; +}; + &mailbox0_cluster0 { status = "okay"; interrupts = <436>;