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b=Sx732rWH77kWBbpP1/0o4ybWYk6ymuwhtJkC+P+YHth25nFyeZckuBaWuCTR2urzRoovzGf2KLtc+X5PSCFEcxeNIHsOt2CisjSFNmWsPEdZOPckYYyeJ/3GpZaE3/cAaSFPGihfoE5BwpMwM9Wl2mmw4tb8VPNVaqxOaoxX6ro= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from DU2PR04MB8822.eurprd04.prod.outlook.com (2603:10a6:10:2e1::11) by DU2PR04MB8917.eurprd04.prod.outlook.com (2603:10a6:10:2e0::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7249.24; Wed, 31 Jan 2024 05:52:00 +0000 Received: from DU2PR04MB8822.eurprd04.prod.outlook.com ([fe80::d45f:4483:c11:68b0]) by DU2PR04MB8822.eurprd04.prod.outlook.com ([fe80::d45f:4483:c11:68b0%7]) with mapi id 15.20.7228.029; Wed, 31 Jan 2024 05:52:00 +0000 From: Xu Yang To: Frank.li@nxp.com, will@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, john.g.garry@oracle.com, jolsa@kernel.org, namhyung@kernel.org, irogers@google.com Cc: linux-imx@nxp.com, mike.leach@linaro.org, leo.yan@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, alexander.shishkin@linux.intel.com, adrian.hunter@intel.com, xu.yang_2@nxp.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, imx@lists.linux.dev Subject: [PATCH v4 3/6] perf: imx_perf: add support for i.MX95 platform Date: Wed, 31 Jan 2024 13:58:08 +0800 Message-Id: <20240131055811.3035741-3-xu.yang_2@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240131055811.3035741-1-xu.yang_2@nxp.com> References: <20240131055811.3035741-1-xu.yang_2@nxp.com> X-ClientProxiedBy: SI2PR02CA0041.apcprd02.prod.outlook.com (2603:1096:4:196::20) To DU2PR04MB8822.eurprd04.prod.outlook.com (2603:10a6:10:2e1::11) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU2PR04MB8822:EE_|DU2PR04MB8917:EE_ X-MS-Office365-Filtering-Correlation-Id: 6f998e44-7f3b-4e37-3973-08dc2220bde4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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This will add support for i.MX95 and enhance the driver to support specific filter handling for it. Usage: For read beat: ~# perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_rd_beat_filt2,counter=3,axi_mask=ID_MASK,axi_id=ID/ ~# perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_rd_beat_filt1,counter=4,axi_mask=ID_MASK,axi_id=ID/ ~# perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_rd_beat_filt0,counter=5,axi_mask=ID_MASK,axi_id=ID/ eg: For edma2: perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_rd_beat_filt0,counter=5,axi_mask=0x00f,axi_id=0x00c/ For write beat: ~# perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_wr_beat_filt,counter=2,axi_mask=ID_MASK,axi_id=ID/ eg: For edma2: perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_wr_beat_filt,counter=2,axi_mask=0x00f,axi_id=0x00c/ Signed-off-by: Xu Yang Reviewed-by: Frank Li --- Changes in v2: - put soc spefific axi filter events to drvdata according to franks suggestions. - adjust pmcfg axi_id and axi_mask config Changes in v3: - no changes Changes in v4: - only contain imx95 parts --- drivers/perf/fsl_imx9_ddr_perf.c | 86 +++++++++++++++++++++++++++++++- 1 file changed, 84 insertions(+), 2 deletions(-) diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c index b1a58e9e1617..85aaaef7212f 100644 --- a/drivers/perf/fsl_imx9_ddr_perf.c +++ b/drivers/perf/fsl_imx9_ddr_perf.c @@ -17,9 +17,19 @@ #define MX93_PMCFG1_RD_BT_FILT_EN BIT(29) #define MX93_PMCFG1_ID_MASK GENMASK(17, 0) +#define MX95_PMCFG1_WR_BEAT_FILT_EN BIT(31) +#define MX95_PMCFG1_RD_BEAT_FILT_EN BIT(30) + #define PMCFG2 0x04 #define MX93_PMCFG2_ID GENMASK(17, 0) +#define PMCFG3 0x08 +#define PMCFG4 0x0C +#define PMCFG5 0x10 +#define PMCFG6 0x14 +#define MX95_PMCFG_ID_MASK GENMASK(9, 0) +#define MX95_PMCFG_ID GENMASK(25, 16) + /* Global control register affects all counters and takes priority over local control registers */ #define PMGC0 0x40 /* Global control register bits */ @@ -240,6 +250,18 @@ static struct attribute *imx93_ddr_perf_events_attrs[] = { NULL, }; +static struct attribute *imx95_ddr_perf_events_attrs[] = { + /* counter2 specific events */ + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_beat_filt, 73), + /* counter3 specific events */ + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt2, 73), + /* counter4 specific events */ + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt1, 73), + /* counter5 specific events */ + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt0, 73), + NULL, +}; + PMU_FORMAT_ATTR(event, "config:0-7"); PMU_FORMAT_ATTR(counter, "config:8-15"); PMU_FORMAT_ATTR(axi_id, "config1:0-17"); @@ -271,8 +293,14 @@ static const struct imx_ddr_devtype_data imx93_devtype_data = { .attrs = imx93_ddr_perf_events_attrs, }; +static const struct imx_ddr_devtype_data imx95_devtype_data = { + .identifier = "imx95", + .attrs = imx95_ddr_perf_events_attrs, +}; + static const struct of_device_id imx_ddr_pmu_dt_ids[] = { { .compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data }, + { .compatible = "fsl,imx95-ddr-pmu", .data = &imx95_devtype_data }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, imx_ddr_pmu_dt_ids); @@ -410,6 +438,56 @@ static void imx93_ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1 writel(pmcfg2, pmu->base + PMCFG2); } +static void imx95_ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1, int cfg2) +{ + u32 pmcfg1, pmcfg, offset = 0; + int event, counter; + + event = cfg & 0x000000FF; + counter = (cfg & 0x0000FF00) >> 8; + + pmcfg1 = readl_relaxed(pmu->base + PMCFG1); + + if (counter == 2 && event == 73) { + pmcfg1 |= MX95_PMCFG1_WR_BEAT_FILT_EN; + offset = PMCFG3; + } else if (counter == 2 && event != 73) { + pmcfg1 &= ~MX95_PMCFG1_WR_BEAT_FILT_EN; + } + + if (counter == 3 && event == 73) { + pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN; + offset = PMCFG4; + } else if (counter == 3 && event != 73) { + pmcfg1 &= ~MX95_PMCFG1_RD_BEAT_FILT_EN; + } + + if (counter == 4 && event == 73) { + pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN; + offset = PMCFG5; + } else if (counter == 4 && event != 73) { + pmcfg1 &= ~MX95_PMCFG1_RD_BEAT_FILT_EN; + } + + if (counter == 5 && event == 73) { + pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN; + offset = PMCFG6; + } else if (counter == 5 && event != 73) { + pmcfg1 &= ~MX95_PMCFG1_RD_BEAT_FILT_EN; + } + + writel(pmcfg1, pmu->base + PMCFG1); + + if (offset) { + pmcfg = readl_relaxed(pmu->base + offset); + pmcfg &= ~(FIELD_PREP(MX95_PMCFG_ID_MASK, 0x3FF) | + FIELD_PREP(MX95_PMCFG_ID, 0x3FF)); + pmcfg |= (FIELD_PREP(MX95_PMCFG_ID_MASK, cfg2) | + FIELD_PREP(MX95_PMCFG_ID, cfg1)); + writel(pmcfg, pmu->base + offset); + } +} + static void ddr_perf_event_update(struct perf_event *event) { struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); @@ -490,8 +568,12 @@ static int ddr_perf_event_add(struct perf_event *event, int flags) hwc->idx = counter; hwc->state |= PERF_HES_STOPPED; - /* read trans, write trans, read beat */ - imx93_ddr_perf_monitor_config(pmu, cfg, cfg1, cfg2); + if (is_imx93(pmu)) + /* read trans, write trans, read beat */ + imx93_ddr_perf_monitor_config(pmu, cfg, cfg1, cfg2); + else + /* write beat, read beat2, read beat1, read beat */ + imx95_ddr_perf_monitor_config(pmu, cfg, cfg1, cfg2); if (flags & PERF_EF_START) ddr_perf_event_start(event, flags);