From patchwork Wed Jan 31 00:37:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Judith Mendez X-Patchwork-Id: 194409 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2087:b0:106:209c:c626 with SMTP id gs7csp1589965dyb; Tue, 30 Jan 2024 16:41:26 -0800 (PST) X-Google-Smtp-Source: AGHT+IGlmRVOPoZRlC724GdW9NcEckzqFSAySfEseoa9UZTUOgcB0J97hW9hT1CugZxzSVlY/1oe X-Received: by 2002:ae9:e70f:0:b0:784:436:5f04 with SMTP id m15-20020ae9e70f000000b0078404365f04mr3098527qka.65.1706661686115; Tue, 30 Jan 2024 16:41:26 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706661686; cv=pass; d=google.com; s=arc-20160816; b=PPvhDGSF1y2Bhd0iul+tZ+SAqXvLmRhsOVV/dLVD0q9SmKisweNucRcHzevTWFeIgF myG9dlgaeldQQeIvO5L8bauRBq6Utb3vLOeGCGqMKe8XLrWgUjdTCzNr6rd8SOAl0bdb XA8qlgN9KHegj1gXXe8cJLxjZe8NyY9RYTbQsl/QnqpQP/jaqNwoce9BnTyWjTPwdIPO Sb1nVNI18Y6Tsnzv/AHcUALjEnpFuZ3u4km76m+Ar5CrEwJ+FhVmFekfPPTvhTn1uEYr +SA7suhc+u6RrYMGSv3TwvA1zOki98Y17PwFDiC/bFpG3HfHoizZLwvxSsnVp+8S8y2Q lG7A== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=eAvv0aSOJvvajgLl06cW3GQaJE/fjuUjp+24JiWk/9A=; fh=OfC2KgLXJHfoAXnVTArbgmBRr8jE8SiTAeK6q5gutbc=; b=yhe9amf2MIZF/OSfR+S2v+vAbz4RWG76WrEoRCIYLYN8C1qCodeGeg8C6eC44YB3Hy SaC3kQ89QufvisBnvscyQdS50GgbMMc92aYrOjSrH1nLLpZWdvl30nnQ94Qc1ImbbX+0 igTQEIlxlrgIlhxR0Rs/2WF3GelD3jqs3zXzMiYD8CvtnNzO1PJWbLW6hBt7YixUr4An Bg4DrHEjjU2vAZ0/zcjO9e6NFTEomTcA5cBQ1INJUhKxFHL05qPDwZgp0qq/BrJh3fCh HpLSPS4e8iOyh/x+qBVToqXExLB5T+UKIgFp0o3PBMEz+NPsm/YnSum7ZvQjySW+crxd oabA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=KqybR8sm; arc=pass (i=1 spf=pass spfdomain=ti.com dkim=pass dkdomain=ti.com dmarc=pass fromdomain=ti.com); spf=pass (google.com: domain of linux-kernel+bounces-45534-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-45534-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com X-Forwarded-Encrypted: i=1; AJvYcCWuXB23Z/a5r1dN9dyehP0WHwucp8StB7f2QpDLP5Aa9wMWMZWDztRNeB6cJOMxMC8OjW4Na8ubarmMA7Q+zAKDmbf8kg== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. [147.75.199.223]) by mx.google.com with ESMTPS id f20-20020a05620a409400b00783fdf24b12si6407945qko.650.2024.01.30.16.41.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jan 2024 16:41:26 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-45534-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) client-ip=147.75.199.223; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=KqybR8sm; arc=pass (i=1 spf=pass spfdomain=ti.com dkim=pass dkdomain=ti.com dmarc=pass fromdomain=ti.com); spf=pass (google.com: domain of linux-kernel+bounces-45534-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-45534-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id D41611C21700 for ; Wed, 31 Jan 2024 00:41:25 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 51855364A8; Wed, 31 Jan 2024 00:37:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="KqybR8sm" Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C07167EEF0; Wed, 31 Jan 2024 00:37:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706661447; cv=none; b=N4v0pVrZ7fDA5DTB2RY9LI0K9IHnD+e8GfEJdYaGabeTpm2l3uUzL/SRxXqpsmW5frKhJEEAtA8QYa3KoIerOx9WXSjqYhA4lYTXRTIAZl5w7XJKNZoCC1B0rjeb/ljJK4QI69XApQNZnmKEnEz3COoPSp93eusPc1DEgtZxIqc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706661447; c=relaxed/simple; bh=uSIQxp/yvzhc4Y6WNYcSagG5vH1bZ4d9JfIO8bJaTNU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=imc3c+Q3fajbf0TC+uS2lOKEct3FIIqP4009hybRt2jkDmXVPcH0qjB1/qkL34l/EfCODFvQekVFyugjsbUI6Bs/P5BLiMYa0Q9uk4sndZceGDF9JGxZMbseT99arks+raG8flB/O1xaM8TGfN8/SFfEByODTjB02kn2Sy/FMls= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=KqybR8sm; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 40V0bFBZ038162; Tue, 30 Jan 2024 18:37:15 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1706661435; bh=eAvv0aSOJvvajgLl06cW3GQaJE/fjuUjp+24JiWk/9A=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=KqybR8smJ/p/0H7qKnezMcn8VadlHDXJutLpExO+9kejCmWDXpdjaSTFytXseRfkS +yOnnoQ3vwy6M8w04s/b4O4DwfBKpGvgJi/cDcflBLv7R8dET/doSPzP9lq+BShT2m gsENvXJmzcTzMPKJ++8w7UYXemzd6XmAl0a0kkD4= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 40V0bFe5030604 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 30 Jan 2024 18:37:15 -0600 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 30 Jan 2024 18:37:15 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 30 Jan 2024 18:37:15 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40V0bEwA026520; Tue, 30 Jan 2024 18:37:15 -0600 From: Judith Mendez To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Adrian Hunter , , , Nishanth Menon , Vignesh Raghavendra , Andrew Davis , Udit Kumar , Roger Quadros , , Randolph Sapp Subject: [RFC PATCH 03/13] drivers: mmc: host: sdhci_am654: Add missing OTAP/ITAP enable Date: Tue, 30 Jan 2024 18:37:04 -0600 Message-ID: <20240131003714.2779593-4-jm@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240131003714.2779593-1-jm@ti.com> References: <20240131003714.2779593-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789564484032115905 X-GMAIL-MSGID: 1789564484032115905 Currently the OTAP/ITAP delay enable functionality is missing in the am654_set_clock function which is used for MMC0 on AM62p and AM64x devices. The OTAP delay is not enabled when timing < SDR25 bus speed mode. The ITAP delay is not enabled for all bus speed modes. Add this OTAP/ITAP delay functionality according to the datasheet [1] OTAPDLYENA and ITAPDLYENA for MMC0. [1] https://www.ti.com/lit/ds/symlink/am62p.pdf Signed-off-by: Judith Mendez --- drivers/mmc/host/sdhci_am654.c | 48 +++++++++++++++++++--------------- 1 file changed, 27 insertions(+), 21 deletions(-) diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c index 0a1ed2ae2eef..35e02f4128a7 100644 --- a/drivers/mmc/host/sdhci_am654.c +++ b/drivers/mmc/host/sdhci_am654.c @@ -143,6 +143,7 @@ struct sdhci_am654_data { struct regmap *base; int otap_del_sel[ARRAY_SIZE(td)]; int itap_del_sel[ARRAY_SIZE(td)]; + u8 itap_del_ena[ARRAY_SIZE(td)]; int clkbuf_sel; int trm_icp; int drv_strength; @@ -171,11 +172,13 @@ struct sdhci_am654_driver_data { }; static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654, - u32 itapdly) + u32 itapdly, u32 enable) { /* Set ITAPCHGWIN before writing to ITAPDLY */ regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0x1 << ITAPCHGWIN_SHIFT); + regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK, + enable << ITAPDLYENA_SHIFT); regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK, itapdly << ITAPDLYSEL_SHIFT); regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); @@ -249,7 +252,8 @@ static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock, return; } - sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing]); + sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing], + sdhci_am654->itap_del_ena[timing]); } static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654, @@ -263,8 +267,8 @@ static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654, mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK; regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); - sdhci_am654_write_itapdly(sdhci_am654, - sdhci_am654->itap_del_sel[timing]); + sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing], + sdhci_am654->itap_del_ena[timing]); } static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) @@ -273,20 +277,17 @@ static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); unsigned char timing = host->mmc->ios.timing; u32 otap_del_sel; - u32 otap_del_ena; u32 mask, val; regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); sdhci_set_clock(host, clock); - /* Setup DLL Output TAP delay */ + /* Setup Output TAP delay */ otap_del_sel = sdhci_am654->otap_del_sel[timing]; - otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0; mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; - val = (otap_del_ena << OTAPDLYENA_SHIFT) | - (otap_del_sel << OTAPDLYSEL_SHIFT); + val = (0x1 << OTAPDLYENA_SHIFT) | (otap_del_sel << OTAPDLYSEL_SHIFT); /* Write to STRBSEL for HS400 speed mode */ if (timing == MMC_TIMING_MMC_HS400) { @@ -319,14 +320,20 @@ static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); unsigned char timing = host->mmc->ios.timing; u32 otap_del_sel; + u32 itap_del_ena; u32 mask, val; - /* Setup DLL Output TAP delay */ + /* Setup Output TAP delay */ otap_del_sel = sdhci_am654->otap_del_sel[timing]; mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; - val = (0x1 << OTAPDLYENA_SHIFT) | - (otap_del_sel << OTAPDLYSEL_SHIFT); + val = (0x1 << OTAPDLYENA_SHIFT) | (otap_del_sel << OTAPDLYSEL_SHIFT); + + itap_del_ena = sdhci_am654->itap_del_ena[timing]; + + mask |= ITAPDLYENA_MASK; + val |= (itap_del_ena << ITAPDLYENA_SHIFT); + regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, @@ -503,12 +510,8 @@ static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host, for (i = 0; i < ITAPDLY_LENGTH; i++) memset(&fail_window[i], 0, sizeof(fail_window[0])); - /* Enable ITAPDLY */ - regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK, - 1 << ITAPDLYENA_SHIFT); - for (itap = 0; itap < ITAPDLY_LENGTH; itap++) { - sdhci_am654_write_itapdly(sdhci_am654, itap); + sdhci_am654_write_itapdly(sdhci_am654, itap, 1); curr_pass = !mmc_send_tuning(host->mmc, opcode, NULL); @@ -532,7 +535,7 @@ static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host, itap = calculate_itap(host, &fail_window[0], fail_index, (sdhci_am654->dll_enable ? true : false)); - sdhci_am654_write_itapdly(sdhci_am654, itap); + sdhci_am654_write_itapdly(sdhci_am654, itap, 1); return 0; } @@ -681,9 +684,12 @@ static int sdhci_am654_get_otap_delay(struct sdhci_host *host, host->mmc->caps2 &= ~td[i].capability; } - if (td[i].itap_binding) - device_property_read_u32(dev, td[i].itap_binding, - &sdhci_am654->itap_del_sel[i]); + if (td[i].itap_binding) { + ret = device_property_read_u32(dev, td[i].itap_binding, + &sdhci_am654->itap_del_sel[i]); + if (!ret) + sdhci_am654->itap_del_ena[i] = 0x1; + } } return 0;