diff mbox series

[v4,16/18] MIPS: mobileye: eyeq5: add reset properties to UARTs

Message ID 20240131-mbly-clk-v4-16-bcd00510d6a0@bootlin.com
State New
Headers
Series Add support for Mobileye EyeQ5 system controller |

Commit Message

Théo Lebrun Jan. 31, 2024, 4:26 p.m. UTC 
  UART nodes have been added to the devicetree by the initial platform
support patch series. Add reset properties now that the reset node is
declared.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
 arch/mips/boot/dts/mobileye/eyeq5.dtsi | 3 +++
 1 file changed, 3 insertions(+)

Comments

Krzysztof Kozlowski Feb. 1, 2024, 9:13 a.m. UTC | #1 
On 31/01/2024 17:26, Théo Lebrun wrote:
> UART nodes have been added to the devicetree by the initial platform
> support patch series. Add reset properties now that the reset node is
> declared.
> 
> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
> ---
>  arch/mips/boot/dts/mobileye/eyeq5.dtsi | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
> index 06e941b0ce10..ece71cafb6ee 100644
> --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi
> +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
> @@ -78,6 +78,7 @@ uart0: serial@800000 {
>  			interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks  = <&uart_clk>, <&occ_periph>;
>  			clock-names = "uartclk", "apb_pclk";
> +			resets = <&reset 0 10>;

You touch the same file. Squash the patch with previous one. It's the
same logical change to add reset to entire SoC. You don't add half of
reset, right?

Best regards,
Krzysztof
Théo Lebrun Feb. 1, 2024, 10:32 a.m. UTC | #2 
Hello,

On Thu Feb 1, 2024 at 10:13 AM CET, Krzysztof Kozlowski wrote:
> On 31/01/2024 17:26, Théo Lebrun wrote:
> > UART nodes have been added to the devicetree by the initial platform
> > support patch series. Add reset properties now that the reset node is
> > declared.
> > 
> > Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
> > ---
> >  arch/mips/boot/dts/mobileye/eyeq5.dtsi | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
> > index 06e941b0ce10..ece71cafb6ee 100644
> > --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi
> > +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
> > @@ -78,6 +78,7 @@ uart0: serial@800000 {
> >  			interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
> >  			clocks  = <&uart_clk>, <&occ_periph>;
> >  			clock-names = "uartclk", "apb_pclk";
> > +			resets = <&reset 0 10>;
>
> You touch the same file. Squash the patch with previous one. It's the
> same logical change to add reset to entire SoC. You don't add half of
> reset, right?

Makes sense. I'll update the commit message with that change.

Thanks,

--
Théo Lebrun, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
diff mbox series

Patch

diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
index 06e941b0ce10..ece71cafb6ee 100644
--- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi
+++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
@@ -78,6 +78,7 @@  uart0: serial@800000 {
 			interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
 			clocks  = <&uart_clk>, <&occ_periph>;
 			clock-names = "uartclk", "apb_pclk";
+			resets = <&reset 0 10>;
 		};
 
 		uart1: serial@900000 {
@@ -88,6 +89,7 @@  uart1: serial@900000 {
 			interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
 			clocks  = <&uart_clk>, <&occ_periph>;
 			clock-names = "uartclk", "apb_pclk";
+			resets = <&reset 0 11>;
 		};
 
 		uart2: serial@a00000 {
@@ -98,6 +100,7 @@  uart2: serial@a00000 {
 			interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
 			clocks  = <&uart_clk>, <&occ_periph>;
 			clock-names = "uartclk", "apb_pclk";
+			resets = <&reset 0 12>;
 		};
 
 		olb: system-controller@e00000 {