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[34.91.112.229]) by smtp.gmail.com with ESMTPSA id hw18-20020a170907a0d200b00a2d7f63dd71sm551280ejc.29.2024.01.26.03.55.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 03:55:20 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, peter.griffin@linaro.org Cc: linux-kernel@vger.kernel.org, kernel-team@android.com, tudor.ambarus@linaro.org, willmcvicker@google.com, daniel.lezcano@linaro.org, tglx@linutronix.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH v3 2/2] arm64: dts: exynos: gs101: sysreg_peric0 needs a clock Date: Fri, 26 Jan 2024 11:55:17 +0000 Message-ID: <20240126115517.1751971-2-andre.draszik@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240126115517.1751971-1-andre.draszik@linaro.org> References: <20240126115517.1751971-1-andre.draszik@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789153963503648370 X-GMAIL-MSGID: 1789153963503648370 Without the clock running, we can not access its registers, and now that we have it, we should add it here so that it gets enabled as and when needed. Update the DTSI accordingly. Signed-off-by: André Draszik --- v3: no changes, resend as a complete series v2: fix subject line --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 412d2866dca7..aaac04df5e65 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -364,6 +364,7 @@ cmu_peric0: clock-controller@10800000 { sysreg_peric0: syscon@10820000 { compatible = "google,gs101-peric0-sysreg", "syscon"; reg = <0x10820000 0x10000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK>; }; pinctrl_peric0: pinctrl@10840000 {