diff mbox series

net: stmmac: dwmac-imx: add clock input support in RMII mode

Message ID 20240126024433.2928223-2-xiaoning.wang@nxp.com
State New
Headers
Series net: stmmac: dwmac-imx: add clock input support in RMII mode |

Commit Message

Clark Wang Jan. 26, 2024, 2:44 a.m. UTC 
  In RMII mode, the default setting is using the 50MHz reference clock
from SoC. The ref_clk pin is output.
If users want to use external or PHY to provide the 50MHz ref clock,
it needs to config the GPR register.
So, add the code to config GPR register to support the clock input.

Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Reviewed-by: Wei Fang <wei.fang@nxp.com>
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

Comments

Andrew Lunn Jan. 29, 2024, 1:51 p.m. UTC | #1 
On Fri, Jan 26, 2024 at 10:44:33AM +0800, Clark Wang wrote:
> In RMII mode, the default setting is using the 50MHz reference clock
> from SoC. The ref_clk pin is output.
> If users want to use external or PHY to provide the 50MHz ref clock,
> it needs to config the GPR register.
> So, add the code to config GPR register to support the clock input.

Hi Clark

You have this threaded to the previous email. That previous email is a
fix, where are this is development of a new feature. So please don't
thread them. Please take a read of:

https://www.kernel.org/doc/html/latest/process/maintainer-netdev.html

You need different Subject lines to indicate which tree these patches
should be applied to.

> 
> Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
> Reviewed-by: Wei Fang <wei.fang@nxp.com>

Signed-of-by comes last.


    Andrew

---
pw-bot: cr
diff mbox series

Patch

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
index 8f730ada71f9..64c5277895e6 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
@@ -36,6 +36,8 @@ 
 #define MX93_GPR_ENET_QOS_INTF_SEL_RMII		(0x4 << 1)
 #define MX93_GPR_ENET_QOS_INTF_SEL_RGMII	(0x1 << 1)
 #define MX93_GPR_ENET_QOS_CLK_GEN_EN		(0x1 << 0)
+#define MX93_GPR_ENET_QOS_CLK_SEL_MASK		BIT_MASK(0)
+#define MX93_GPR_CLK_SEL_OFFSET			(4)
 
 #define DMA_BUS_MODE			0x00001000
 #define DMA_BUS_MODE_SFT_RESET		(0x1 << 0)
@@ -108,13 +110,22 @@  imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat)
 static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat)
 {
 	struct imx_priv_data *dwmac = plat_dat->bsp_priv;
-	int val;
+	int val, ret;
 
 	switch (plat_dat->mac_interface) {
 	case PHY_INTERFACE_MODE_MII:
 		val = MX93_GPR_ENET_QOS_INTF_SEL_MII;
 		break;
 	case PHY_INTERFACE_MODE_RMII:
+		if (dwmac->rmii_refclk_ext) {
+			ret = regmap_update_bits(dwmac->intf_regmap,
+						 dwmac->intf_reg_off +
+						 MX93_GPR_CLK_SEL_OFFSET,
+						 MX93_GPR_ENET_QOS_CLK_SEL_MASK,
+						 0);
+			if (ret)
+				return ret;
+		}
 		val = MX93_GPR_ENET_QOS_INTF_SEL_RMII;
 		break;
 	case PHY_INTERFACE_MODE_RGMII: