Message ID | 20240125140139.3616119-2-andre.draszik@linaro.org |
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State | New |
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[34.91.112.229]) by smtp.gmail.com with ESMTPSA id r17-20020a1709067fd100b00a2c7d34157asm1048170ejs.180.2024.01.25.06.01.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:01:42 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= <andre.draszik@linaro.org> To: linux-kernel@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, peter.griffin@linaro.org Cc: kernel-team@android.com, tudor.ambarus@linaro.org, willmcvicker@google.com, daniel.lezcano@linaro.org, tglx@linutronix.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 2/2] arm64: dts: exynos: gs101: sysreg_peric1 needs a clock Date: Thu, 25 Jan 2024 14:01:39 +0000 Message-ID: <20240125140139.3616119-2-andre.draszik@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125140139.3616119-1-andre.draszik@linaro.org> References: <20240125140139.3616119-1-andre.draszik@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: <linux-kernel.vger.kernel.org> List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789071304953876620 X-GMAIL-MSGID: 1789071304953876620 |
Series |
[1/2] dt-bindings: samsung: exynos-sysreg: gs101-peric0 requires a clock
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Commit Message
André Draszik
Jan. 25, 2024, 2:01 p.m. UTC
Without the clock running, we can not access its registers, and now
that we have it, we should add it here so that it gets enabled as
and when needed.
Update the DTSI accordingly.
Signed-off-by: André Draszik <andre.draszik@linaro.org>
---
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 1 +
1 file changed, 1 insertion(+)
Comments
> [PATCH v2] arm64: dts: exynos: gs101: sysreg_peric0 needs a clock
Sorry for copy/paste error in the subject :-(
I've sent an update in https://lore.kernel.org/all/20240125140644.3617587-1-andre.draszik@linaro.org/
Cheers,
Andre'
On 25/01/2024 15:10, André Draszik wrote: >> [PATCH v2] arm64: dts: exynos: gs101: sysreg_peric0 needs a clock > > Sorry for copy/paste error in the subject :-( > > I've sent an update in https://lore.kernel.org/all/20240125140644.3617587-1-andre.draszik@linaro.org/ Which makes it impossible to apply (at least with usual workflow): Grabbing thread from lore.kernel.org/all/20240125140139.3616119-1-andre.draszik@linaro.org/t.mbox.gz Checking for newer revisions Grabbing search results from lore.kernel.org Analyzing 4 messages in the thread Will use the latest revision: v2 You can pick other revisions using the -vN flag Checking attestation on all messages, may take a moment... --- ✓ [PATCH v2] arm64: dts: exynos: gs101: sysreg_peric0 needs a clock + Link: https://lore.kernel.org/r/20240125140644.3617587-1-andre.draszik@linaro.org + Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- ✓ Signed: DKIM/linaro.org --- Total patches: 1 --- Applying: arm64: dts: exynos: gs101: sysreg_peric0 needs a clock --- Patchwork: setting state on patchwork.kernel.org/linux-samsung-soc -> under-review : [v2] arm64: dts: exynos: gs101: sysreg_peric0 needs a clock Please do not invent your own workflows of handling patches. Each submission must be: 1. In separate thread, not linked to something else, 2. Complete. I await for v3. Best regards, Krzysztof
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 412d2866dca7..aaac04df5e65 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -364,6 +364,7 @@ cmu_peric0: clock-controller@10800000 { sysreg_peric0: syscon@10820000 { compatible = "google,gs101-peric0-sysreg", "syscon"; reg = <0x10820000 0x10000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK>; }; pinctrl_peric0: pinctrl@10840000 {