Message ID | 20240124-pcie-aux-clk-fix-v1-2-d8a4852b6ba6@linaro.org |
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State | New |
Headers |
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Series |
Drop PCIE_AUX_CLK from the PCIe PHY nodes of Qcom SoCs
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Commit Message
Manivannan Sadhasivam
Jan. 24, 2024, 7:36 a.m. UTC
PCIe PHY hw doesn't require PCIE_AUX_CLK for functioning. This clock is
only required by the PCIe controller. Hence drop it from pcie_phy node.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 5e1277fea725..1767e5abd76d 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -283,11 +283,9 @@ pcie_phy: phy@84000 { reg = <0x0 0x00084000 0x0 0x1000>; status = "disabled"; - clocks = <&gcc GCC_PCIE0_AUX_CLK>, - <&gcc GCC_PCIE0_AHB_CLK>, + clocks = <&gcc GCC_PCIE0_AHB_CLK>, <&gcc GCC_PCIE0_PIPE_CLK>; - clock-names = "aux", - "cfg_ahb", + clock-names = "cfg_ahb", "pipe"; clock-output-names = "gcc_pcie0_pipe_clk_src";