Message ID | 20240124-pcie-aux-clk-fix-v1-11-d8a4852b6ba6@linaro.org |
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State | New |
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Series |
Drop PCIE_AUX_CLK from the PCIe PHY nodes of Qcom SoCs
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Commit Message
Manivannan Sadhasivam
Jan. 24, 2024, 7:36 a.m. UTC
PCIe PHY hw doesn't require PCIE_AUX_CLK for functioning. This clock is
only required by the PCIe controller. Hence drop it from pcie_phy node.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 01e4dfc4babd..1e0091dabaf1 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1830,13 +1830,11 @@ pcie0_phy: phy@1c06000 { compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; reg = <0 0x01c06000 0 0x2000>; - clocks = <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&gcc GCC_PCIE_0_CLKREF_EN>, <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK>; - clock-names = "aux", - "cfg_ahb", + clock-names = "cfg_ahb", "ref", "rchng", "pipe";