Message ID | 20240120012948.8836-6-semen.protsenko@linaro.org |
---|---|
State | New |
Headers |
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Fri, 19 Jan 2024 17:29:53 -0800 (PST) Received: from localhost ([136.62.192.75]) by smtp.gmail.com with ESMTPSA id yl13-20020a05687c218d00b002109874642esm1096224oab.44.2024.01.19.17.29.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Jan 2024 17:29:52 -0800 (PST) From: Sam Protsenko <semen.protsenko@linaro.org> To: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Andi Shyti <andi.shyti@kernel.org>, Mark Brown <broonie@kernel.org>, Rob Herring <robh+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org> Cc: Alim Akhtar <alim.akhtar@samsung.com>, Sylwester Nawrocki <s.nawrocki@samsung.com>, Tomasz Figa <tomasz.figa@gmail.com>, Chanwoo Choi <cw00.choi@samsung.com>, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH 5/7] spi: s3c64xx: Add Exynos850 support Date: Fri, 19 Jan 2024 19:29:46 -0600 Message-Id: <20240120012948.8836-6-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240120012948.8836-1-semen.protsenko@linaro.org> References: <20240120012948.8836-1-semen.protsenko@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: <linux-kernel.vger.kernel.org> List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788571095521441177 X-GMAIL-MSGID: 1788571095521441177 |
Series |
arm64: exynos: Enable SPI for Exynos850
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Commit Message
Sam Protsenko
Jan. 20, 2024, 1:29 a.m. UTC
Add SPI port configuration for Exynos850 SoC. It has 3 USI blocks which
can be configured in SPI mode:
* spi_0: BLK_PERI_SPI_0 (0x13940000)
* spi_1: BLK_ALIVE_USI_CMGP00 (0x11d00000)
* spi_2: BLK_ALIVE_USI_CMGP01 (0x11d20000)
SPI FIFO depth is 64 bytes for all those SPI blocks, so the
fifo_lvl_mask value is set to 0x7f. All blocks have DIV_4 as the
default internal clock divider, and an internal loopback mode to run
a loopback test.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
---
drivers/spi/spi-s3c64xx.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
Comments
On 1/20/24 01:29, Sam Protsenko wrote: > Add SPI port configuration for Exynos850 SoC. It has 3 USI blocks which > can be configured in SPI mode: > > * spi_0: BLK_PERI_SPI_0 (0x13940000) > * spi_1: BLK_ALIVE_USI_CMGP00 (0x11d00000) > * spi_2: BLK_ALIVE_USI_CMGP01 (0x11d20000) > > SPI FIFO depth is 64 bytes for all those SPI blocks, so the > .fifo_lvl_mask value is set to 0x7f. All blocks have DIV_4 as the > default internal clock divider, and an internal loopback mode to run > a loopback test. > > Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> > --- > drivers/spi/spi-s3c64xx.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c > index 0e48ffd499b9..f7d623ad6ac3 100644 > --- a/drivers/spi/spi-s3c64xx.c > +++ b/drivers/spi/spi-s3c64xx.c > @@ -1461,6 +1461,17 @@ static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = { > .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, > }; > > +static const struct s3c64xx_spi_port_config exynos850_spi_port_config = { > + .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f }, I'll come with a follow up patch on top of this. Having the dt alias used as an index in the fifo_lvl_mask to determine the FIFO depth is wrong. Not only because of the dependency on the alias, but also because the fifo_lvl_mask value does not reflect the FIFO level reg field. Playing with what we have now is ok by me, I find the patch good. > + .rx_lvl_offset = 15, > + .tx_st_done = 25, > + .clk_div = 4, > + .high_speed = true, > + .clk_from_cmu = true, > + .has_loopback = true, > + .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, > +}; > + > static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = { > .fifo_lvl_mask = { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff, 0x7f, > 0x7f, 0x7f, 0x7f, 0x7f}, > @@ -1515,6 +1526,9 @@ static const struct of_device_id s3c64xx_spi_dt_match[] = { > { .compatible = "samsung,exynos5433-spi", > .data = (void *)&exynos5433_spi_port_config, > }, > + { .compatible = "samsung,exynos850-spi", > + .data = (void *)&exynos850_spi_port_config, > + }, > { .compatible = "samsung,exynosautov9-spi", > .data = (void *)&exynosautov9_spi_port_config, > },
On Wed, Jan 24, 2024 at 12:49 AM Tudor Ambarus <tudor.ambarus@linaro.org> wrote: > > > > On 1/20/24 01:29, Sam Protsenko wrote: > > Add SPI port configuration for Exynos850 SoC. It has 3 USI blocks which > > can be configured in SPI mode: > > > > * spi_0: BLK_PERI_SPI_0 (0x13940000) > > * spi_1: BLK_ALIVE_USI_CMGP00 (0x11d00000) > > * spi_2: BLK_ALIVE_USI_CMGP01 (0x11d20000) > > > > SPI FIFO depth is 64 bytes for all those SPI blocks, so the > > .fifo_lvl_mask value is set to 0x7f. All blocks have DIV_4 as the > > default internal clock divider, and an internal loopback mode to run > > a loopback test. > > > > Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> > > Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> > > > --- > > drivers/spi/spi-s3c64xx.c | 14 ++++++++++++++ > > 1 file changed, 14 insertions(+) > > > > diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c > > index 0e48ffd499b9..f7d623ad6ac3 100644 > > --- a/drivers/spi/spi-s3c64xx.c > > +++ b/drivers/spi/spi-s3c64xx.c > > @@ -1461,6 +1461,17 @@ static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = { > > .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, > > }; > > > > +static const struct s3c64xx_spi_port_config exynos850_spi_port_config = { > > + .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f }, > > I'll come with a follow up patch on top of this. Having the dt alias > used as an index in the fifo_lvl_mask to determine the FIFO depth is > wrong. Not only because of the dependency on the alias, but also because > the fifo_lvl_mask value does not reflect the FIFO level reg field. > Playing with what we have now is ok by me, I find the patch good. > Yeah, we just have to make sure all our patches are taken in the correct order, to avoid any possible conflicts. > > + .rx_lvl_offset = 15, > > + .tx_st_done = 25, > > + .clk_div = 4, > > + .high_speed = true, > > + .clk_from_cmu = true, > > + .has_loopback = true, > > + .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, > > +}; > > + > > static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = { > > .fifo_lvl_mask = { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff, 0x7f, > > 0x7f, 0x7f, 0x7f, 0x7f}, > > @@ -1515,6 +1526,9 @@ static const struct of_device_id s3c64xx_spi_dt_match[] = { > > { .compatible = "samsung,exynos5433-spi", > > .data = (void *)&exynos5433_spi_port_config, > > }, > > + { .compatible = "samsung,exynos850-spi", > > + .data = (void *)&exynos850_spi_port_config, > > + }, > > { .compatible = "samsung,exynosautov9-spi", > > .data = (void *)&exynosautov9_spi_port_config, > > },
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 0e48ffd499b9..f7d623ad6ac3 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1461,6 +1461,17 @@ static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = { .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, }; +static const struct s3c64xx_spi_port_config exynos850_spi_port_config = { + .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f }, + .rx_lvl_offset = 15, + .tx_st_done = 25, + .clk_div = 4, + .high_speed = true, + .clk_from_cmu = true, + .has_loopback = true, + .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, +}; + static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = { .fifo_lvl_mask = { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, @@ -1515,6 +1526,9 @@ static const struct of_device_id s3c64xx_spi_dt_match[] = { { .compatible = "samsung,exynos5433-spi", .data = (void *)&exynos5433_spi_port_config, }, + { .compatible = "samsung,exynos850-spi", + .data = (void *)&exynos850_spi_port_config, + }, { .compatible = "samsung,exynosautov9-spi", .data = (void *)&exynosautov9_spi_port_config, },