[v2] soc: qcom: rpmh-rsc: Enhance check for VREG in-flight request

Message ID 20240119-rpmh-rsc-fixes-v2-1-e42c0a9e36f0@quicinc.com
State New
Headers
Series [v2] soc: qcom: rpmh-rsc: Enhance check for VREG in-flight request |

Commit Message

Maulik Shah Jan. 19, 2024, 8:26 a.m. UTC
  Each RPMh VREG accelerator resource has 3 or 4 contiguous 4-byte aligned
addresses associated with it. These control voltage, enable state, mode,
and in legacy targets, voltage headroom. The current in-flight request
checking logic looks for exact address matches. Requests for different
addresses of the same RPMh resource as thus not detected as in-flight.

Enhance the in-flight request check for VREG requests by ignoring the
address offset. This ensures that only one request is allowed to be
in-flight for a given VREG resource. This is needed to avoid scenarios
where request commands are carried out by RPMh hardware out-of-order
leading to LDO regulator over-current protection triggering.

Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
Signed-off-by: Elliot Berman <quic_eberman@quicinc.com>
---
Changes in v2:
- Use GENMASK() and FIELD_GET()
- Link to v1: https://lore.kernel.org/r/20240117-rpmh-rsc-fixes-v1-1-71ee4f8f72a4@quicinc.com
---
 drivers/soc/qcom/rpmh-rsc.c | 21 ++++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)


---
base-commit: 943b9f0ab2cfbaea148dd6ac279957eb08b96904
change-id: 20240117-rpmh-rsc-fixes-6c43c7051828

Best regards,
  

Comments

Bryan O'Donoghue Jan. 19, 2024, 10:34 a.m. UTC | #1
On 19/01/2024 08:26, Maulik Shah wrote:
> Each RPMh VREG accelerator resource has 3 or 4 contiguous 4-byte aligned
> addresses associated with it. These control voltage, enable state, mode,
> and in legacy targets, voltage headroom. The current in-flight request
> checking logic looks for exact address matches. Requests for different
> addresses of the same RPMh resource as thus not detected as in-flight.

This commit log implies you are fixing a bug.

Can you do some inspection of the git commit log and figure out where to 
backport this change to ?

Your change would apply to 40482e4f73640d but a quick pass on the logic 
in check_for_req_inflight() shows its probably _applicable_ to 
658628e7ef78e8

>   /*
>    * Here's a high level overview of how all the registers in RPMH work
>    * together:
> @@ -557,7 +568,15 @@ static int check_for_req_inflight(struct rsc_drv *drv, struct tcs_group *tcs,
>   		for_each_set_bit(j, &curr_enabled, MAX_CMDS_PER_TCS) {
>   			addr = read_tcs_cmd(drv, drv->regs[RSC_DRV_CMD_ADDR], i, j);
>   			for (k = 0; k < msg->num_cmds; k++) {
> -				if (addr == msg->cmds[k].addr)
> +				/*
> +				 * Each RPMh VREG accelerator resource has 3 or 4 contiguous 4-byte
> +				 * aligned addresses associated with it. Ignore the offset to check
> +				 * for in-flight VREG requests.
> +				 */
> +				if (ACCL_TYPE(msg->cmds[k].addr) == HW_ACCL_VREG &&
> +				    VREG_ADDR(msg->cmds[k].addr) == VREG_ADDR(addr))
> +					return -EBUSY;
> +				else if (addr == msg->cmds[k].addr)

Consider removing the /* comment */ if it helps to apply the change 
earlier than 658628e7ef78e8.

---
bod
  
Bryan O'Donoghue Jan. 19, 2024, 11:30 a.m. UTC | #2
On 19/01/2024 10:34, Bryan O'Donoghue wrote:
> Consider removing the /* comment */ if it helps to apply the change 
> earlier than 658628e7ef78e8.
> 
> ---
> bod
> 

Earlier than 40482e4f73640d !

---
bod
  
Andrew Halaney Jan. 19, 2024, 3:47 p.m. UTC | #3
On Fri, Jan 19, 2024 at 01:56:54PM +0530, Maulik Shah wrote:
> Each RPMh VREG accelerator resource has 3 or 4 contiguous 4-byte aligned
> addresses associated with it. These control voltage, enable state, mode,
> and in legacy targets, voltage headroom. The current in-flight request
> checking logic looks for exact address matches. Requests for different
> addresses of the same RPMh resource as thus not detected as in-flight.
> 
> Enhance the in-flight request check for VREG requests by ignoring the
> address offset. This ensures that only one request is allowed to be
> in-flight for a given VREG resource. This is needed to avoid scenarios
> where request commands are carried out by RPMh hardware out-of-order
> leading to LDO regulator over-current protection triggering.
> 
> Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
> Signed-off-by: Elliot Berman <quic_eberman@quicinc.com>

Just noticed I commented on v1 when v2 was already out, sorry. Copy
pasting this just to keep it on the latest thread:

Two minor things:

    1. Does this deserve a Fixes: tag?
    2. The Signed-off-by chain here confuses me, you sent the patch
       so your SOB should be last, but then that makes me believe Elliot
       was the author which I don't think is reflected here (no From:
       line). Please read [0] for a bit more details

[0] https://www.kernel.org/doc/html/latest/process/submitting-patches.html#developer-s-certificate-of-origin-1-1

> ---
> Changes in v2:
> - Use GENMASK() and FIELD_GET()
> - Link to v1: https://lore.kernel.org/r/20240117-rpmh-rsc-fixes-v1-1-71ee4f8f72a4@quicinc.com
> ---
>  drivers/soc/qcom/rpmh-rsc.c | 21 ++++++++++++++++++++-
>  1 file changed, 20 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c
> index a021dc71807b..e480cde783fe 100644
> --- a/drivers/soc/qcom/rpmh-rsc.c
> +++ b/drivers/soc/qcom/rpmh-rsc.c
> @@ -1,11 +1,13 @@
>  // SPDX-License-Identifier: GPL-2.0
>  /*
>   * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
>   */
>  
>  #define pr_fmt(fmt) "%s " fmt, KBUILD_MODNAME
>  
>  #include <linux/atomic.h>
> +#include <linux/bitfield.h>
>  #include <linux/cpu_pm.h>
>  #include <linux/delay.h>
>  #include <linux/interrupt.h>
> @@ -91,6 +93,15 @@ enum {
>  #define CMD_STATUS_ISSUED		BIT(8)
>  #define CMD_STATUS_COMPL		BIT(16)
>  
> +#define ACCL_TYPE(addr)			FIELD_GET(GENMASK(19, 16), addr)
> +#define VREG_ADDR(addr)			FIELD_GET(GENMASK(19, 4), addr)
> +
> +enum {
> +	HW_ACCL_CLK = 0x3,
> +	HW_ACCL_VREG,
> +	HW_ACCL_BUS,
> +};
> +
>  /*
>   * Here's a high level overview of how all the registers in RPMH work
>   * together:
> @@ -557,7 +568,15 @@ static int check_for_req_inflight(struct rsc_drv *drv, struct tcs_group *tcs,
>  		for_each_set_bit(j, &curr_enabled, MAX_CMDS_PER_TCS) {
>  			addr = read_tcs_cmd(drv, drv->regs[RSC_DRV_CMD_ADDR], i, j);
>  			for (k = 0; k < msg->num_cmds; k++) {
> -				if (addr == msg->cmds[k].addr)
> +				/*
> +				 * Each RPMh VREG accelerator resource has 3 or 4 contiguous 4-byte
> +				 * aligned addresses associated with it. Ignore the offset to check
> +				 * for in-flight VREG requests.
> +				 */
> +				if (ACCL_TYPE(msg->cmds[k].addr) == HW_ACCL_VREG &&
> +				    VREG_ADDR(msg->cmds[k].addr) == VREG_ADDR(addr))
> +					return -EBUSY;
> +				else if (addr == msg->cmds[k].addr)
>  					return -EBUSY;
>  			}
>  		}
> 
> ---
> base-commit: 943b9f0ab2cfbaea148dd6ac279957eb08b96904
> change-id: 20240117-rpmh-rsc-fixes-6c43c7051828
> 
> Best regards,
> -- 
> Maulik Shah <quic_mkshah@quicinc.com>
> 
>
  
Elliot Berman Jan. 19, 2024, 5:59 p.m. UTC | #4
On 1/19/2024 7:47 AM, Andrew Halaney wrote:
> On Fri, Jan 19, 2024 at 01:56:54PM +0530, Maulik Shah wrote:
>> Each RPMh VREG accelerator resource has 3 or 4 contiguous 4-byte aligned
>> addresses associated with it. These control voltage, enable state, mode,
>> and in legacy targets, voltage headroom. The current in-flight request
>> checking logic looks for exact address matches. Requests for different
>> addresses of the same RPMh resource as thus not detected as in-flight.
>>
>> Enhance the in-flight request check for VREG requests by ignoring the
>> address offset. This ensures that only one request is allowed to be
>> in-flight for a given VREG resource. This is needed to avoid scenarios
>> where request commands are carried out by RPMh hardware out-of-order
>> leading to LDO regulator over-current protection triggering.
>>
>> Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
>> Signed-off-by: Elliot Berman <quic_eberman@quicinc.com>
> 
> Just noticed I commented on v1 when v2 was already out, sorry. Copy
> pasting this just to keep it on the latest thread:
> 
> Two minor things:
> 
>     1. Does this deserve a Fixes: tag?
>     2. The Signed-off-by chain here confuses me, you sent the patch
>        so your SOB should be last, but then that makes me believe Elliot
>        was the author which I don't think is reflected here (no From:
>        line). Please read [0] for a bit more details
> 
> [0] https://www.kernel.org/doc/html/latest/process/submitting-patches.html#developer-s-certificate-of-origin-1-1
> 

Maulik's S-o-B should be last. This change was authored by him
in our downstream driver and this change was pointed out as
also being a fix for the upstream driver. I helped rebase/apply
the change to upstream to test and shared patch back with him
for posting to the list.

When he got the rebased patch, my S-o-B would've been last, but
now need to be updated again so his is last.

>> ---
>> Changes in v2:
>> - Use GENMASK() and FIELD_GET()
>> - Link to v1: https://lore.kernel.org/r/20240117-rpmh-rsc-fixes-v1-1-71ee4f8f72a4@quicinc.com
>> ---
>>  drivers/soc/qcom/rpmh-rsc.c | 21 ++++++++++++++++++++-
>>  1 file changed, 20 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c
>> index a021dc71807b..e480cde783fe 100644
>> --- a/drivers/soc/qcom/rpmh-rsc.c
>> +++ b/drivers/soc/qcom/rpmh-rsc.c
>> @@ -1,11 +1,13 @@
>>  // SPDX-License-Identifier: GPL-2.0
>>  /*
>>   * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
>>   */
>>  
>>  #define pr_fmt(fmt) "%s " fmt, KBUILD_MODNAME
>>  
>>  #include <linux/atomic.h>
>> +#include <linux/bitfield.h>
>>  #include <linux/cpu_pm.h>
>>  #include <linux/delay.h>
>>  #include <linux/interrupt.h>
>> @@ -91,6 +93,15 @@ enum {
>>  #define CMD_STATUS_ISSUED		BIT(8)
>>  #define CMD_STATUS_COMPL		BIT(16)
>>  
>> +#define ACCL_TYPE(addr)			FIELD_GET(GENMASK(19, 16), addr)
>> +#define VREG_ADDR(addr)			FIELD_GET(GENMASK(19, 4), addr)
>> +
>> +enum {
>> +	HW_ACCL_CLK = 0x3,
>> +	HW_ACCL_VREG,
>> +	HW_ACCL_BUS,
>> +};
>> +
>>  /*
>>   * Here's a high level overview of how all the registers in RPMH work
>>   * together:
>> @@ -557,7 +568,15 @@ static int check_for_req_inflight(struct rsc_drv *drv, struct tcs_group *tcs,
>>  		for_each_set_bit(j, &curr_enabled, MAX_CMDS_PER_TCS) {
>>  			addr = read_tcs_cmd(drv, drv->regs[RSC_DRV_CMD_ADDR], i, j);
>>  			for (k = 0; k < msg->num_cmds; k++) {
>> -				if (addr == msg->cmds[k].addr)
>> +				/*
>> +				 * Each RPMh VREG accelerator resource has 3 or 4 contiguous 4-byte
>> +				 * aligned addresses associated with it. Ignore the offset to check
>> +				 * for in-flight VREG requests.
>> +				 */
>> +				if (ACCL_TYPE(msg->cmds[k].addr) == HW_ACCL_VREG &&
>> +				    VREG_ADDR(msg->cmds[k].addr) == VREG_ADDR(addr))
>> +					return -EBUSY;
>> +				else if (addr == msg->cmds[k].addr)
>>  					return -EBUSY;
>>  			}
>>  		}
>>
>> ---
>> base-commit: 943b9f0ab2cfbaea148dd6ac279957eb08b96904
>> change-id: 20240117-rpmh-rsc-fixes-6c43c7051828
>>
>> Best regards,
>> -- 
>> Maulik Shah <quic_mkshah@quicinc.com>
>>
>>
>
  
Konrad Dybcio Jan. 20, 2024, 12:18 a.m. UTC | #5
On 1/19/24 09:26, Maulik Shah wrote:
> Each RPMh VREG accelerator resource has 3 or 4 contiguous 4-byte aligned
> addresses associated with it. These control voltage, enable state, mode,
> and in legacy targets, voltage headroom. The current in-flight request
> checking logic looks for exact address matches. Requests for different
> addresses of the same RPMh resource as thus not detected as in-flight.
> 
> Enhance the in-flight request check for VREG requests by ignoring the
> address offset. This ensures that only one request is allowed to be
> in-flight for a given VREG resource. This is needed to avoid scenarios
> where request commands are carried out by RPMh hardware out-of-order
> leading to LDO regulator over-current protection triggering.
> 
> Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
> Signed-off-by: Elliot Berman <quic_eberman@quicinc.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

As others have pointed out, a fixes: would be in order.

If you're going to resend, please name the enum but no biggie

Konrad
  
Bjorn Andersson Jan. 28, 2024, 3:43 a.m. UTC | #6
On Fri, Jan 19, 2024 at 01:56:54PM +0530, Maulik Shah wrote:
> Each RPMh VREG accelerator resource has 3 or 4 contiguous 4-byte aligned
> addresses associated with it. These control voltage, enable state, mode,
> and in legacy targets, voltage headroom. The current in-flight request
> checking logic looks for exact address matches. Requests for different
> addresses of the same RPMh resource as thus not detected as in-flight.
> 
> Enhance the in-flight request check for VREG requests by ignoring the
> address offset. This ensures that only one request is allowed to be
> in-flight for a given VREG resource. This is needed to avoid scenarios
> where request commands are carried out by RPMh hardware out-of-order
> leading to LDO regulator over-current protection triggering.
> 
> Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
> Signed-off-by: Elliot Berman <quic_eberman@quicinc.com>

The s-o-b chain doesn't look right.

> ---
> Changes in v2:
> - Use GENMASK() and FIELD_GET()
> - Link to v1: https://lore.kernel.org/r/20240117-rpmh-rsc-fixes-v1-1-71ee4f8f72a4@quicinc.com
> ---
>  drivers/soc/qcom/rpmh-rsc.c | 21 ++++++++++++++++++++-
>  1 file changed, 20 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c
> index a021dc71807b..e480cde783fe 100644
> --- a/drivers/soc/qcom/rpmh-rsc.c
> +++ b/drivers/soc/qcom/rpmh-rsc.c
> @@ -1,11 +1,13 @@
>  // SPDX-License-Identifier: GPL-2.0
>  /*
>   * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
>   */
>  
>  #define pr_fmt(fmt) "%s " fmt, KBUILD_MODNAME
>  
>  #include <linux/atomic.h>
> +#include <linux/bitfield.h>
>  #include <linux/cpu_pm.h>
>  #include <linux/delay.h>
>  #include <linux/interrupt.h>
> @@ -91,6 +93,15 @@ enum {
>  #define CMD_STATUS_ISSUED		BIT(8)
>  #define CMD_STATUS_COMPL		BIT(16)
>  
> +#define ACCL_TYPE(addr)			FIELD_GET(GENMASK(19, 16), addr)

Command DB is there so we don't have to make assumptions about the
addresses of resources. As such, I dislike this define.

> +#define VREG_ADDR(addr)			FIELD_GET(GENMASK(19, 4), addr)
> +
> +enum {
> +	HW_ACCL_CLK = 0x3,
> +	HW_ACCL_VREG,
> +	HW_ACCL_BUS,

We already define these in the kernel, but with different names:
CMD_DB_HW_ARC, CMD_DB_HW_VRM, CMD_DB_HW_BCM. I see no reason to use
different names for the same thing.

> +};
> +
>  /*
>   * Here's a high level overview of how all the registers in RPMH work
>   * together:
> @@ -557,7 +568,15 @@ static int check_for_req_inflight(struct rsc_drv *drv, struct tcs_group *tcs,
>  		for_each_set_bit(j, &curr_enabled, MAX_CMDS_PER_TCS) {
>  			addr = read_tcs_cmd(drv, drv->regs[RSC_DRV_CMD_ADDR], i, j);
>  			for (k = 0; k < msg->num_cmds; k++) {
> -				if (addr == msg->cmds[k].addr)
> +				/*
> +				 * Each RPMh VREG accelerator resource has 3 or 4 contiguous 4-byte
> +				 * aligned addresses associated with it. Ignore the offset to check
> +				 * for in-flight VREG requests.
> +				 */
> +				if (ACCL_TYPE(msg->cmds[k].addr) == HW_ACCL_VREG &&
> +				    VREG_ADDR(msg->cmds[k].addr) == VREG_ADDR(addr))

I'm sure this work, at least for some targets, but I don't fancy
encoding this information here. It feels like a hack.

Furthermore, I really would like TP_printk() of trace_rpmh_send_msg() to
be able to resolve the symbolic names for VRMs as well, and it would
need the same information...

Please consider how we can query command db for the type and/or grouping
information.

Regards,
Bjorn

> +					return -EBUSY;
> +				else if (addr == msg->cmds[k].addr)
>  					return -EBUSY;
>  			}
>  		}
> 
> ---
> base-commit: 943b9f0ab2cfbaea148dd6ac279957eb08b96904
> change-id: 20240117-rpmh-rsc-fixes-6c43c7051828
> 
> Best regards,
> -- 
> Maulik Shah <quic_mkshah@quicinc.com>
>
  
Maulik Shah Jan. 29, 2024, 6:20 a.m. UTC | #7
Hi,

On 1/28/2024 9:13 AM, Bjorn Andersson wrote:
> On Fri, Jan 19, 2024 at 01:56:54PM +0530, Maulik Shah wrote:

>>
>> Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
>> Signed-off-by: Elliot Berman <quic_eberman@quicinc.com>
> 
> The s-o-b chain doesn't look right.

I will fix in v3.

> 
>> ---
>>   
>> +#define ACCL_TYPE(addr)			FIELD_GET(GENMASK(19, 16), addr)
> 
> Command DB is there so we don't have to make assumptions about the
> addresses of resources. As such, I dislike this define.

sure i will consider querying command db for resource type.

> 
>> +#define VREG_ADDR(addr)			FIELD_GET(GENMASK(19, 4), addr)
>> +
>> +enum {
>> +	HW_ACCL_CLK = 0x3,
>> +	HW_ACCL_VREG,
>> +	HW_ACCL_BUS,
> 
> We already define these in the kernel, but with different names:
> CMD_DB_HW_ARC, CMD_DB_HW_VRM, CMD_DB_HW_BCM. I see no reason to use
> different names for the same thing.
> 
>> +};

Right, I missed it, With querying cmd-db would not need this enum.

>> +
>>   /*
>>    * Here's a high level overview of how all the registers in RPMH work
>>    * together:
>> @@ -557,7 +568,15 @@ static int check_for_req_inflight(struct rsc_drv *drv, struct tcs_group *tcs,
>>   		for_each_set_bit(j, &curr_enabled, MAX_CMDS_PER_TCS) {
>>   			addr = read_tcs_cmd(drv, drv->regs[RSC_DRV_CMD_ADDR], i, j);
>>   			for (k = 0; k < msg->num_cmds; k++) {
>> -				if (addr == msg->cmds[k].addr)
>> +				/*
>> +				 * Each RPMh VREG accelerator resource has 3 or 4 contiguous 4-byte
>> +				 * aligned addresses associated with it. Ignore the offset to check
>> +				 * for in-flight VREG requests.
>> +				 */
>> +				if (ACCL_TYPE(msg->cmds[k].addr) == HW_ACCL_VREG &&
>> +				    VREG_ADDR(msg->cmds[k].addr) == VREG_ADDR(addr))
> 
> I'm sure this work, at least for some targets, but I don't fancy
> encoding this information here. It feels like a hack.
> 
> Furthermore, I really would like TP_printk() of trace_rpmh_send_msg() to
> be able to resolve the symbolic names for VRMs as well, and it would
> need the same information...

I can update in separate patch for trace_() to resolve symbolic names.

> 
> Please consider how we can query command db for the type and/or grouping
> information.

Sure, i will update in v3 to query command db for the type.

Thanks,
Maulik
  
Maulik Shah Jan. 29, 2024, 6:27 a.m. UTC | #8
Hi,

On 1/19/2024 9:17 PM, Andrew Halaney wrote:

>> Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
>> Signed-off-by: Elliot Berman <quic_eberman@quicinc.com>
> 
> Just noticed I commented on v1 when v2 was already out, sorry. Copy
> pasting this just to keep it on the latest thread:
> 
> Two minor things:
> 
>      1. Does this deserve a Fixes: tag?
>      2. The Signed-off-by chain here confuses me, you sent the patch
>         so your SOB should be last, but then that makes me believe Elliot
>         was the author which I don't think is reflected here (no From:
>         line). Please read [0] for a bit more details
> 
> [0] https://www.kernel.org/doc/html/latest/process/submitting-patches.html#developer-s-certificate-of-origin-1-1

Yes, this looks good to have patch, will include fixes:  tag and will 
fix SOB in v3.

Thanks,
Maulik
  

Patch

diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c
index a021dc71807b..e480cde783fe 100644
--- a/drivers/soc/qcom/rpmh-rsc.c
+++ b/drivers/soc/qcom/rpmh-rsc.c
@@ -1,11 +1,13 @@ 
 // SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #define pr_fmt(fmt) "%s " fmt, KBUILD_MODNAME
 
 #include <linux/atomic.h>
+#include <linux/bitfield.h>
 #include <linux/cpu_pm.h>
 #include <linux/delay.h>
 #include <linux/interrupt.h>
@@ -91,6 +93,15 @@  enum {
 #define CMD_STATUS_ISSUED		BIT(8)
 #define CMD_STATUS_COMPL		BIT(16)
 
+#define ACCL_TYPE(addr)			FIELD_GET(GENMASK(19, 16), addr)
+#define VREG_ADDR(addr)			FIELD_GET(GENMASK(19, 4), addr)
+
+enum {
+	HW_ACCL_CLK = 0x3,
+	HW_ACCL_VREG,
+	HW_ACCL_BUS,
+};
+
 /*
  * Here's a high level overview of how all the registers in RPMH work
  * together:
@@ -557,7 +568,15 @@  static int check_for_req_inflight(struct rsc_drv *drv, struct tcs_group *tcs,
 		for_each_set_bit(j, &curr_enabled, MAX_CMDS_PER_TCS) {
 			addr = read_tcs_cmd(drv, drv->regs[RSC_DRV_CMD_ADDR], i, j);
 			for (k = 0; k < msg->num_cmds; k++) {
-				if (addr == msg->cmds[k].addr)
+				/*
+				 * Each RPMh VREG accelerator resource has 3 or 4 contiguous 4-byte
+				 * aligned addresses associated with it. Ignore the offset to check
+				 * for in-flight VREG requests.
+				 */
+				if (ACCL_TYPE(msg->cmds[k].addr) == HW_ACCL_VREG &&
+				    VREG_ADDR(msg->cmds[k].addr) == VREG_ADDR(addr))
+					return -EBUSY;
+				else if (addr == msg->cmds[k].addr)
 					return -EBUSY;
 			}
 		}