diff mbox series

[v2] irqchip/loongson-eiointc: Refine irq affinity setting during resume

Message ID 20240116080555.409215-1-maobibo@loongson.cn
State New
Headers
Series [v2] irqchip/loongson-eiointc: Refine irq affinity setting during resume |

Commit Message

maobibo Jan. 16, 2024, 8:05 a.m. UTC 
  During suspend and resume, other CPUs are hot-unpluged and IRQs are
migrated to CPU0. So it is not necessary to restore irq affinity for
eiointc irq controller.

Also there is some optimization for the interrupt dispatch function
eiointc_irq_dispatch. There are 256 IRQs supported for eiointc, eiointc
irq handler reads the bitmap and find pending irqs when irq happens.
So there are four times of consecutive iocsr_read64 operations for the
total 256 bits to find all pending irqs. If the pending bitmap is zero,
it means that there is no pending irq for the this irq bitmap range,
we can skip handling to avoid some useless operations sush as clearing
hw ISR.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 Changes in v2:
   Modify changelog and comments
---
 drivers/irqchip/irq-loongson-eiointc.c | 29 +++++++++++---------------
 1 file changed, 12 insertions(+), 17 deletions(-)


base-commit: 052d534373b7ed33712a63d5e17b2b6cdbce84fd

Comments

Sergey Shtylyov Jan. 16, 2024, 8:17 a.m. UTC | #1 
On 1/16/24 11:05 AM, Bibo Mao wrote:

> During suspend and resume, other CPUs are hot-unpluged and IRQs are
> migrated to CPU0. So it is not necessary to restore irq affinity for
> eiointc irq controller.
> 
> Also there is some optimization for the interrupt dispatch function
> eiointc_irq_dispatch. There are 256 IRQs supported for eiointc, eiointc
> irq handler reads the bitmap and find pending irqs when irq happens.
> So there are four times of consecutive iocsr_read64 operations for the
> total 256 bits to find all pending irqs. If the pending bitmap is zero,
> it means that there is no pending irq for the this irq bitmap range,
> we can skip handling to avoid some useless operations sush as clearing

    s/sush/such/?

> hw ISR.

   This sounds like you need 2 patches to deal with 2 separate issues...

> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
[...]

MBR, Sergey
maobibo Jan. 16, 2024, 8:26 a.m. UTC | #2 
Sergey,

Thanks for reviewing my patch.
I reply inline.

On 2024/1/16 下午4:17, Sergey Shtylyov wrote:
> On 1/16/24 11:05 AM, Bibo Mao wrote:
> 
>> During suspend and resume, other CPUs are hot-unpluged and IRQs are
>> migrated to CPU0. So it is not necessary to restore irq affinity for
>> eiointc irq controller.
>>
>> Also there is some optimization for the interrupt dispatch function
>> eiointc_irq_dispatch. There are 256 IRQs supported for eiointc, eiointc
>> irq handler reads the bitmap and find pending irqs when irq happens.
>> So there are four times of consecutive iocsr_read64 operations for the
>> total 256 bits to find all pending irqs. If the pending bitmap is zero,
>> it means that there is no pending irq for the this irq bitmap range,
>> we can skip handling to avoid some useless operations sush as clearing
> 
>      s/sush/such/?
will fix.

> 
>> hw ISR.
> 
>     This sounds like you need 2 patches to deal with 2 separate issues...
Sure, I will separate it into 2 patches in next version.

Regards
Bibo Mao
> 
>> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
> [...]
> 
> MBR, Sergey
>
diff mbox series

Patch

diff --git a/drivers/irqchip/irq-loongson-eiointc.c b/drivers/irqchip/irq-loongson-eiointc.c
index 1623cd779175..1a25e0613d50 100644
--- a/drivers/irqchip/irq-loongson-eiointc.c
+++ b/drivers/irqchip/irq-loongson-eiointc.c
@@ -198,6 +198,17 @@  static void eiointc_irq_dispatch(struct irq_desc *desc)
 
 	for (i = 0; i < eiointc_priv[0]->vec_count / VEC_COUNT_PER_REG; i++) {
 		pending = iocsr_read64(EIOINTC_REG_ISR + (i << 3));
+
+		/*
+		 * Get pending eiointc irq from bitmap status, there are 4 times
+		 * consecutive iocsr_read64 operations for 256 IRQs.
+		 *
+		 * Skip handling if pending bitmap is zero
+		 */
+		if (!pending)
+			continue;
+
+		/* Clear the IRQs */
 		iocsr_write64(pending, EIOINTC_REG_ISR + (i << 3));
 		while (pending) {
 			int bit = __ffs(pending);
@@ -241,7 +252,7 @@  static int eiointc_domain_alloc(struct irq_domain *domain, unsigned int virq,
 	int ret;
 	unsigned int i, type;
 	unsigned long hwirq = 0;
-	struct eiointc *priv = domain->host_data;
+	struct eiointc_priv *priv = domain->host_data;
 
 	ret = irq_domain_translate_onecell(domain, arg, &hwirq, &type);
 	if (ret)
@@ -304,23 +315,7 @@  static int eiointc_suspend(void)
 
 static void eiointc_resume(void)
 {
-	int i, j;
-	struct irq_desc *desc;
-	struct irq_data *irq_data;
-
 	eiointc_router_init(0);
-
-	for (i = 0; i < nr_pics; i++) {
-		for (j = 0; j < eiointc_priv[0]->vec_count; j++) {
-			desc = irq_resolve_mapping(eiointc_priv[i]->eiointc_domain, j);
-			if (desc && desc->handle_irq && desc->handle_irq != handle_bad_irq) {
-				raw_spin_lock(&desc->lock);
-				irq_data = irq_domain_get_irq_data(eiointc_priv[i]->eiointc_domain, irq_desc_get_irq(desc));
-				eiointc_set_irq_affinity(irq_data, irq_data->common->affinity, 0);
-				raw_spin_unlock(&desc->lock);
-			}
-		}
-	}
 }
 
 static struct syscore_ops eiointc_syscore_ops = {