| Message ID | 20240112094632.66310-11-angelogioacchino.delregno@collabora.com |
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From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: linux-mediatek@lists.infradead.org
Cc: robh+dt@kernel.org,
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Subject: [PATCH 10/15] arm64: dts: mediatek: radxa-nio-12l: Enable PCI-Express
0 for USB HUB
Date: Fri, 12 Jan 2024 10:46:27 +0100
Message-ID: <20240112094632.66310-11-angelogioacchino.delregno@collabora.com>
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| Series |
MediaTek: Introduce MT8395 Radxa NIO 12L devicetree
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Commit Message
AngeloGioacchino Del Regno
Jan. 12, 2024, 9:46 a.m. UTC
Enable the PCIe0 controller, providing part of the USB connectivity
found on this board through a USB HUB connected over PCI-Express.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../boot/dts/mediatek/mt8395-radxa-nio-12l.dts | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts index 5a9e33013209..dbde2c7b3c64 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts @@ -564,6 +564,15 @@ pins-irq { }; }; + pcie0_default_pins: pcie0-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO19__FUNC_WAKEN>, + <PINMUX_GPIO20__FUNC_PERSTN>, + <PINMUX_GPIO21__FUNC_CLKREQN>; + bias-pull-up; + }; + }; + uart0_pins: uart0-pins { pins-bus { pinmux = <PINMUX_GPIO98__FUNC_UTXD0>, @@ -583,6 +592,12 @@ pins-wifi-vreg-en { }; }; +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_pins>; + status = "okay"; +}; + &pmic { interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; };