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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by MWH0EPF000971E2.mail.protection.outlook.com (10.167.243.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7181.14 via Frontend Transport; Fri, 12 Jan 2024 00:07:05 +0000 Received: from ruby-95f9host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Thu, 11 Jan 2024 18:07:02 -0600 From: Suravee Suthikulpanit To: , , , CC: , , , , , , , , , , Suravee Suthikulpanit Subject: [RFCv2 PATCH 3/7] iommu/amd: Update PASID, GATS, and GLX feature related macros Date: Thu, 11 Jan 2024 18:06:42 -0600 Message-ID: <20240112000646.98001-4-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240112000646.98001-1-suravee.suthikulpanit@amd.com> References: <20240112000646.98001-1-suravee.suthikulpanit@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E2:EE_|SN7PR12MB7449:EE_ X-MS-Office365-Filtering-Correlation-Id: ba335f5c-149e-457e-19f9-08dc13026946 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jan 2024 00:07:05.5425 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ba335f5c-149e-457e-19f9-08dc13026946 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E2.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7449 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787841038442520476 X-GMAIL-MSGID: 1787841038442520476 Clean up and reorder them according to the bit index. There is no functional change. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 2 +- drivers/iommu/amd/amd_iommu_types.h | 13 +++++++------ drivers/iommu/amd/init.c | 8 ++++---- 3 files changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index bbed268e8abc..108253edbeb0 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -106,7 +106,7 @@ static inline bool check_feature2(u64 mask) static inline int check_feature_gpt_level(void) { - return ((amd_iommu_efr >> FEATURE_GATS_SHIFT) & FEATURE_GATS_MASK); + return ((amd_iommu_efr & FEATURE_GATS_MASK) >> FEATURE_GATS_SHIFT); } static inline bool amd_iommu_gt_ppr_supported(void) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h index ff56c857f6ad..f8baa8d88832 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -93,8 +93,6 @@ #define FEATURE_GA BIT_ULL(7) #define FEATURE_HE BIT_ULL(8) #define FEATURE_PC BIT_ULL(9) -#define FEATURE_GATS_SHIFT (12) -#define FEATURE_GATS_MASK (3ULL) #define FEATURE_GAM_VAPIC BIT_ULL(21) #define FEATURE_GIOSUP BIT_ULL(48) #define FEATURE_HASUP BIT_ULL(49) @@ -102,11 +100,14 @@ #define FEATURE_HDSUP BIT_ULL(52) #define FEATURE_SNP BIT_ULL(63) -#define FEATURE_PASID_SHIFT 32 -#define FEATURE_PASID_MASK (0x1fULL << FEATURE_PASID_SHIFT) +#define FEATURE_GATS_SHIFT 12 +#define FEATURE_GATS_MASK (0x03ULL << FEATURE_GATS_SHIFT) -#define FEATURE_GLXVAL_SHIFT 14 -#define FEATURE_GLXVAL_MASK (0x03ULL << FEATURE_GLXVAL_SHIFT) +#define FEATURE_GLX_SHIFT 14 +#define FEATURE_GLX_MASK (0x03ULL << FEATURE_GLX_SHIFT) + +#define FEATURE_PASMAX_SHIFT 32 +#define FEATURE_PASMAX_MASK (0x1FULL << FEATURE_PASMAX_SHIFT) /* Extended Feature 2 Bits */ #define FEATURE_SNPAVICSUP_SHIFT 5 diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 959820ccfbcc..e84c69fe13d4 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -2080,14 +2080,14 @@ static int __init iommu_init_pci(struct amd_iommu *iommu) int glxval; u64 pasmax; - pasmax = amd_iommu_efr & FEATURE_PASID_MASK; - pasmax >>= FEATURE_PASID_SHIFT; + pasmax = amd_iommu_efr & FEATURE_PASMAX_MASK; + pasmax >>= FEATURE_PASMAX_SHIFT; iommu->iommu.max_pasids = (1 << (pasmax + 1)) - 1; BUG_ON(iommu->iommu.max_pasids & ~PASID_MASK); - glxval = amd_iommu_efr & FEATURE_GLXVAL_MASK; - glxval >>= FEATURE_GLXVAL_SHIFT; + glxval = amd_iommu_efr & FEATURE_GLX_MASK; + glxval >>= FEATURE_GLX_SHIFT; if (amd_iommu_max_glx_val == -1) amd_iommu_max_glx_val = glxval;