Message ID | 20240111081914.3123-4-adrian.hunter@intel.com |
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State | New |
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[2604:1380:40f1:3f00::1]) by mx.google.com with ESMTPS id b13-20020a6567cd000000b005c680fbab22si581425pgs.509.2024.01.11.00.24.45 for <ouuuleilei@gmail.com> (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 00:24:45 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-23202-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) client-ip=2604:1380:40f1:3f00::1; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="kI2nw5f/"; spf=pass (google.com: domain of linux-kernel+bounces-23202-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-23202-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sy.mirrors.kernel.org (Postfix) with ESMTPS id B906BB27399 for <ouuuleilei@gmail.com>; Thu, 11 Jan 2024 08:20:39 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4E48CFBEE; Thu, 11 Jan 2024 08:19:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="kI2nw5f/" Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13EC0F9EF; Thu, 11 Jan 2024 08:19:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704961186; x=1736497186; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tu9E652ONSBsccr80I5sJ0ZIDYKgQL8NQOkj5aWqOCA=; b=kI2nw5f/QJwfoBL6cn0yDZarQTF4u5kJKjD4u/f8wc8NxMjTh3M/0iNM bbB2uiKusVWsLYa1fXOs0mXZcclPZwFL9j/iiEb62VRsBWFgT1VolLSoj WCSuWecZDSLb3ke/IEZjmpQ2XH0oeq0t5VuAK+5r6v8LahGaLyiTVhlDy 5kIZH6YALVziU/lbaEuE9o6IR5LNcoW/T/2+4CkSAcmkGJT0DfPH+oK6N oLuYjxX+alHc65QqX1j72zIZMPhkuUtr7bfXVWlBB/xpI5+gj7SbpkuD2 k4Is0SWIAGVo25QQBJG9KNImZi5i90dIf8ugl3djpyFOpjuiBDp+W3tqt A==; X-IronPort-AV: E=McAfee;i="6600,9927,10949"; a="465166381" X-IronPort-AV: E=Sophos;i="6.04,185,1695711600"; d="scan'208";a="465166381" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jan 2024 00:19:45 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10949"; a="925923034" X-IronPort-AV: E=Sophos;i="6.04,185,1695711600"; d="scan'208";a="925923034" Received: from ahunter6-mobl1.ger.corp.intel.com (HELO ahunter-VirtualBox.home\044ger.corp.intel.com) ([10.252.52.224]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jan 2024 00:19:40 -0800 From: Adrian Hunter <adrian.hunter@intel.com> To: Peter Zijlstra <peterz@infradead.org> Cc: Ingo Molnar <mingo@redhat.com>, Mark Rutland <mark.rutland@arm.com>, Alexander Shishkin <alexander.shishkin@linux.intel.com>, Heiko Carstens <hca@linux.ibm.com>, Thomas Richter <tmricht@linux.ibm.com>, Hendrik Brueckner <brueckner@linux.ibm.com>, Suzuki K Poulose <suzuki.poulose@arm.com>, Mike Leach <mike.leach@linaro.org>, James Clark <james.clark@arm.com>, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, Yicong Yang <yangyicong@hisilicon.com>, Jonathan Cameron <jonathan.cameron@huawei.com>, Will Deacon <will@kernel.org>, Arnaldo Carvalho de Melo <acme@kernel.org>, Jiri Olsa <jolsa@kernel.org>, Namhyung Kim <namhyung@kernel.org>, Ian Rogers <irogers@google.com>, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Subject: [PATCH V4 03/11] perf tools: Enable evsel__is_aux_event() to work for ARM/ARM64 Date: Thu, 11 Jan 2024 10:19:06 +0200 Message-Id: <20240111081914.3123-4-adrian.hunter@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111081914.3123-1-adrian.hunter@intel.com> References: <20240111081914.3123-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: <linux-kernel.vger.kernel.org> List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: 8bit X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787781694468613831 X-GMAIL-MSGID: 1787781694468613831 |
Series |
perf/core: Add ability for an event to "pause" or "resume" AUX area tracing
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Commit Message
Adrian Hunter
Jan. 11, 2024, 8:19 a.m. UTC
Set pmu->auxtrace on ARM/ARM64 AUX area PMUs. evsel__is_aux_event() needs
the setting to identify AUX area tracing selected events.
Currently, the features that use evsel__is_aux_event() are used only by
Intel PT, but that may change in the future.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
---
tools/perf/arch/arm/util/pmu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tools/perf/arch/arm/util/pmu.c b/tools/perf/arch/arm/util/pmu.c index 7f3af3b97f3b..88fbd366246d 100644 --- a/tools/perf/arch/arm/util/pmu.c +++ b/tools/perf/arch/arm/util/pmu.c @@ -19,14 +19,17 @@ void perf_pmu__arch_init(struct perf_pmu *pmu __maybe_unused) #ifdef HAVE_AUXTRACE_SUPPORT if (!strcmp(pmu->name, CORESIGHT_ETM_PMU_NAME)) { /* add ETM default config here */ + pmu->auxtrace = true; pmu->selectable = true; pmu->perf_event_attr_init_default = cs_etm_get_default_config; #if defined(__aarch64__) } else if (strstarts(pmu->name, ARM_SPE_PMU_NAME)) { + pmu->auxtrace = true; pmu->selectable = true; pmu->is_uncore = false; pmu->perf_event_attr_init_default = arm_spe_pmu_default_config; } else if (strstarts(pmu->name, HISI_PTT_PMU_NAME)) { + pmu->auxtrace = true; pmu->selectable = true; #endif }