diff mbox series

[v2,2/3] dt-bindings: clock: qcom,gcc-sm8150: Add gcc video resets for sm8150

Message ID 20240111-sm8150-dfs-support-v2-2-6edb44c83d3b@quicinc.com
State New
Headers
Series clk: qcom: Add dfs support for QUPv3 RCGs on SM8150 |

Commit Message

Satya Priya Kakitapalli Jan. 11, 2024, 6:32 a.m. UTC 
  Add gcc video axic, axi0 and axi1 resets for the global clock controller
on sm8150.

Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
---
 include/dt-bindings/clock/qcom,gcc-sm8150.h | 3 +++
 1 file changed, 3 insertions(+)

Comments

Krzysztof Kozlowski Jan. 11, 2024, 7:59 a.m. UTC | #1 
On 11/01/2024 07:32, Satya Priya Kakitapalli wrote:
> Add gcc video axic, axi0 and axi1 resets for the global clock controller
> on sm8150.
> 
> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
> ---

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/include/dt-bindings/clock/qcom,gcc-sm8150.h b/include/dt-bindings/clock/qcom,gcc-sm8150.h
index dfefd5e8bf6e..921a33f24d33 100644
--- a/include/dt-bindings/clock/qcom,gcc-sm8150.h
+++ b/include/dt-bindings/clock/qcom,gcc-sm8150.h
@@ -239,6 +239,9 @@ 
 #define GCC_USB30_PRIM_BCR					26
 #define GCC_USB30_SEC_BCR					27
 #define GCC_USB_PHY_CFG_AHB2PHY_BCR				28
+#define GCC_VIDEO_AXIC_CLK_BCR					29
+#define GCC_VIDEO_AXI0_CLK_BCR					30
+#define GCC_VIDEO_AXI1_CLK_BCR					31
 
 /* GCC GDSCRs */
 #define PCIE_0_GDSC						0