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Wed, 10 Jan 2024 13:32:23 +0000 Received: from BJSPR01MB0561.CHNPR01.prod.partner.outlook.cn ([fe80::3862:65b4:c857:c4a6]) by BJSPR01MB0561.CHNPR01.prod.partner.outlook.cn ([fe80::3862:65b4:c857:c4a6%4]) with mapi id 15.20.7135.033; Wed, 10 Jan 2024 13:32:23 +0000 From: Sia Jee Heng To: kernel@esmil.dk, conor@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, emil.renner.berthing@canonical.com, hal.feng@starfivetech.com, xingyu.wu@starfivetech.com Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, jeeheng.sia@starfivetech.com, leyfoon.tan@starfivetech.com, Krzysztof Kozlowski Subject: [RFC v3 11/16] dt-bindings: clock: Add StarFive JH8100 South-West clock and reset generator Date: Wed, 10 Jan 2024 21:31:23 +0800 Message-Id: <20240110133128.286657-12-jeeheng.sia@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240110133128.286657-1-jeeheng.sia@starfivetech.com> References: <20240110133128.286657-1-jeeheng.sia@starfivetech.com> X-ClientProxiedBy: BJXPR01CA0067.CHNPR01.prod.partner.outlook.cn (2406:e500:c211:12::34) To BJSPR01MB0561.CHNPR01.prod.partner.outlook.cn (2406:e500:c211:f::16) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BJSPR01MB0561:EE_|BJSPR01MB0626:EE_ X-MS-Office365-Filtering-Correlation-Id: 004116c4-307d-422c-197c-08dc11e093fd X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Sia Jee Heng Reviewed-by: Ley Foon Tan Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/starfive,jh8100-swcrg.yaml | 64 +++++++++++++++++++ .../dt-bindings/clock/starfive,jh8100-crg.h | 12 ++++ .../dt-bindings/reset/starfive,jh8100-crg.h | 8 +++ 3 files changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-swcrg.yaml diff --git a/Documentation/devicetree/bindings/clock/starfive,jh8100-swcrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh8100-swcrg.yaml new file mode 100644 index 000000000000..287dff7e91e3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh8100-swcrg.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh8100-swcrg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH8100 South-West Clock And Reset Generator + +maintainers: + - Sia Jee Heng + +properties: + compatible: + const: starfive,jh8100-swcrg + + reg: + maxItems: 1 + + clocks: + items: + - description: APB_BUS clock from SYSCRG + - description: VDEC_ROOT clock from SYSCRG + - description: FLEXNOC1 clock from SYSCRG + + clock-names: + items: + - const: apb_bus + - const: vdec_root + - const: flexnoc1 + + '#clock-cells': + const: 1 + description: + See for valid indices. + + '#reset-cells': + const: 1 + description: + See for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@12720000 { + compatible = "starfive,jh8100-swcrg"; + reg = <0x12720000 0x10000>; + clocks = <&syscrg JH8100_SYSCLK_APB_BUS>, + <&syscrg JH8100_SYSCLK_VDEC_ROOT>, + <&syscrg JH8100_SYSCLK_FLEXNOC1>; + clock-names = "apb_bus", "vdec_root", "flexnoc1"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jh8100-crg.h b/include/dt-bindings/clock/starfive,jh8100-crg.h index c37b42f3eacd..7b337c1495be 100644 --- a/include/dt-bindings/clock/starfive,jh8100-crg.h +++ b/include/dt-bindings/clock/starfive,jh8100-crg.h @@ -339,4 +339,16 @@ #define JH8100_NECLK_CAN1_ICG_EN 173 #define JH8100_NECLK_SMBUS0_ICG_EN 174 +/* SWCRG clocks */ +#define JH8100_SWCLK_JPEG_AXI 0 +#define JH8100_SWCLK_VC9000DJ_AXI 1 +#define JH8100_SWCLK_VC9000DJ_VDEC 2 +#define JH8100_SWCLK_VC9000DJ_APB 3 +#define JH8100_SWCLK_VDEC_AXI 4 +#define JH8100_SWCLK_VC9000D_AXI 5 +#define JH8100_SWCLK_VC9000D_VDEC 6 +#define JH8100_SWCLK_VC9000D_APB 7 +#define JH8100_SWCLK_JPEG_ICG_EN 8 +#define JH8100_SWCLK_VDEC_ICG_EN 9 + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ */ diff --git a/include/dt-bindings/reset/starfive,jh8100-crg.h b/include/dt-bindings/reset/starfive,jh8100-crg.h index 30a99c78341a..de4f25dc301d 100644 --- a/include/dt-bindings/reset/starfive,jh8100-crg.h +++ b/include/dt-bindings/reset/starfive,jh8100-crg.h @@ -91,4 +91,12 @@ #define JH8100_NERST_SYS_IOMUX_E 48 #define JH8100_NERST_DUBHE_TVSENSOR 49 +/* + * SWCRG resets: assert0 + */ +#define JH8100_SWRST_PRESETN 0 +#define JH8100_SWRST_VC9000DJ 1 +#define JH8100_SWRST_VC9000D 2 +#define JH8100_SWRST_DDR_TVSENSOR 3 + #endif /* __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ */