@@ -7,6 +7,7 @@
#include <dt-bindings/clock/qcom,apss-ipq.h>
#include <dt-bindings/clock/qcom,ipq5332-gcc.h>
+#include <dt-bindings/clock/qcom,ipq5332-nsscc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
@@ -492,15 +493,376 @@ nsscc: clock-controller@39b00000{
clocks = <&cmn_pll_nss_200m_clk>,
<&cmn_pll_nss_300m_clk>,
<&gcc GPLL0_OUT_AUX>,
- <0>,
- <0>,
- <0>,
- <0>,
+ <&uniphys 0>,
+ <&uniphys 1>,
+ <&uniphys 2>,
+ <&uniphys 3>,
<&xo_board>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
+
+ qcom_ppe: qcom-ppe@3a000000 {
+ compatible = "qcom,ipq5332-ppe";
+ reg = <0x3a000000 0xb00000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "okay";
+
+ clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>,
+ <&gcc GCC_CMN_12GPLL_SYS_CLK>,
+ <&gcc GCC_UNIPHY0_SYS_CLK>,
+ <&gcc GCC_UNIPHY1_SYS_CLK>,
+ <&gcc GCC_UNIPHY0_AHB_CLK>,
+ <&gcc GCC_UNIPHY1_AHB_CLK>,
+ <&gcc GCC_NSSCC_CLK>,
+ <&gcc GCC_NSSNOC_SNOC_CLK>,
+ <&gcc GCC_NSSNOC_SNOC_1_CLK>,
+ <&gcc GCC_IM_SLEEP_CLK>,
+ <&nsscc NSS_CC_PPE_SWITCH_CLK>,
+ <&nsscc NSS_CC_PPE_SWITCH_CFG_CLK>,
+ <&nsscc NSS_CC_NSSNOC_PPE_CLK>,
+ <&nsscc NSS_CC_NSSNOC_PPE_CFG_CLK>,
+ <&nsscc NSS_CC_PPE_EDMA_CLK>,
+ <&nsscc NSS_CC_PPE_EDMA_CFG_CLK>,
+ <&nsscc NSS_CC_PPE_SWITCH_IPE_CLK>,
+ <&nsscc NSS_CC_PPE_SWITCH_BTQ_CLK>,
+ <&nsscc NSS_CC_PORT1_MAC_CLK>,
+ <&nsscc NSS_CC_PORT2_MAC_CLK>,
+ <&nsscc NSS_CC_PORT1_RX_CLK>,
+ <&nsscc NSS_CC_PORT1_TX_CLK>,
+ <&nsscc NSS_CC_PORT2_RX_CLK>,
+ <&nsscc NSS_CC_PORT2_TX_CLK>,
+ <&nsscc NSS_CC_UNIPHY_PORT1_RX_CLK>,
+ <&nsscc NSS_CC_UNIPHY_PORT1_TX_CLK>,
+ <&nsscc NSS_CC_UNIPHY_PORT2_RX_CLK>,
+ <&nsscc NSS_CC_UNIPHY_PORT2_TX_CLK>;
+ clock-names = "cmn_ahb",
+ "cmn_sys",
+ "uniphy0_sys",
+ "uniphy1_sys",
+ "uniphy0_ahb",
+ "uniphy1_ahb",
+ "gcc_nsscc",
+ "gcc_nssnoc_snoc",
+ "gcc_nssnoc_snoc_1",
+ "gcc_im_sleep",
+ "nss_ppe",
+ "nss_ppe_cfg",
+ "nssnoc_ppe",
+ "nssnoc_ppe_cfg",
+ "nss_edma",
+ "nss_edma_cfg",
+ "nss_ppe_ipe",
+ "nss_ppe_btq",
+ "port1_mac",
+ "port2_mac",
+ "nss_port1_rx",
+ "nss_port1_tx",
+ "nss_port2_rx",
+ "nss_port2_tx",
+ "uniphy_port1_rx",
+ "uniphy_port1_tx",
+ "uniphy_port2_rx",
+ "uniphy_port2_tx";
+
+ resets = <&nsscc NSS_CC_PPE_BCR>,
+ <&gcc GCC_UNIPHY0_SYS_CLK_ARES>,
+ <&gcc GCC_UNIPHY1_SYS_CLK_ARES>,
+ <&gcc GCC_UNIPHY0_AHB_CLK_ARES>,
+ <&gcc GCC_UNIPHY1_AHB_CLK_ARES>,
+ <&gcc GCC_UNIPHY0_XPCS_ARES>,
+ <&gcc GCC_UNIPHY1_XPCS_ARES>,
+ <&gcc GCC_UNIPHY0_BCR>,
+ <&gcc GCC_UNIPHY1_BCR>,
+ <&nsscc NSS_CC_UNIPHY_PORT1_RX_CLK_ARES>,
+ <&nsscc NSS_CC_UNIPHY_PORT1_TX_CLK_ARES>,
+ <&nsscc NSS_CC_UNIPHY_PORT2_RX_CLK_ARES>,
+ <&nsscc NSS_CC_UNIPHY_PORT2_TX_CLK_ARES>,
+ <&nsscc NSS_CC_PORT1_RX_CLK_ARES>,
+ <&nsscc NSS_CC_PORT1_TX_CLK_ARES>,
+ <&nsscc NSS_CC_PORT2_RX_CLK_ARES>,
+ <&nsscc NSS_CC_PORT2_TX_CLK_ARES>,
+ <&nsscc NSS_CC_PORT1_MAC_CLK_ARES>,
+ <&nsscc NSS_CC_PORT2_MAC_CLK_ARES>;
+ reset-names = "ppe",
+ "uniphy0_sys",
+ "uniphy1_sys",
+ "uniphy0_ahb",
+ "uniphy1_ahb",
+ "uniphy0_xpcs",
+ "uniphy1_xpcs",
+ "uniphy0_soft",
+ "uniphy1_soft",
+ "uniphy_port1_rx",
+ "uniphy_port1_tx",
+ "uniphy_port2_rx",
+ "uniphy_port2_tx",
+ "nss_port1_rx",
+ "nss_port1_tx",
+ "nss_port2_rx",
+ "nss_port2_tx",
+ "nss_port1_mac",
+ "nss_port2_mac";
+
+ uniphys: qcom-uniphy@7a00000 {
+ reg = <0x7a00000 0x10000>,
+ <0x7a10000 0x10000>;
+ #clock-cells = <0x1>;
+ clock-output-names = "uniphy0_gcc_rx_clk",
+ "uniphy0_gcc_tx_clk",
+ "uniphy1_gcc_rx_clk",
+ "uniphy1_gcc_tx_clk";
+ };
+
+ tdm-config {
+ /*
+ * qcom,tdm-bm-config =
+ * <valid egress port second_valid second_port>;
+ */
+ qcom,tdm-bm-config = <1 0 2 0 0>,
+ <1 1 0 0 0>,
+ <1 0 1 0 0>,
+ <1 1 1 0 0>,
+ <1 0 2 0 0>,
+ <1 1 2 0 0>,
+ <1 0 0 0 0>,
+ <1 1 0 0 0>,
+ <1 0 2 0 0>,
+ <1 1 1 0 0>,
+ <1 0 1 0 0>,
+ <1 1 2 0 0>,
+ <1 0 0 0 0>,
+ <1 1 0 0 0>,
+ <1 0 1 0 0>,
+ <1 1 1 0 0>,
+ <1 0 2 0 0>,
+ <1 1 2 0 0>,
+ <1 0 1 0 0>,
+ <1 1 0 0 0>,
+ <1 0 2 0 0>,
+ <1 1 1 0 0>,
+ <1 0 0 0 0>,
+ <1 1 2 0 0>,
+ <1 0 2 0 0>,
+ <1 1 0 0 0>,
+ <1 0 1 0 0>,
+ <1 1 1 0 0>,
+ <1 0 0 0 0>,
+ <1 1 2 0 0>,
+ <1 0 1 0 0>,
+ <0 0 0 0 0>;
+
+ /*
+ * qcom,tdm-port-scheduler-config =
+ * <ensch_bmp ensch_port desch_port
+ * desch_second_valid desch_second_port>;
+ */
+ qcom,tdm-port-scheduler-config = <0x0 2 0 0 0>,
+ <0x0 1 2 0 0>,
+ <0x0 0 1 0 0>,
+ <0x0 0 2 0 0>,
+ <0x0 1 0 0 0>,
+ <0x0 2 1 0 0>,
+ <0x0 0 2 0 0>,
+ <0x0 0 1 0 0>,
+ <0x0 0 2 0 0>,
+ <0x0 0 1 0 0>;
+ };
+
+ buffer-management-config {
+ /* qcom,group-config = <group group_buf>; */
+ qcom,group-config = <0 240>;
+ /*
+ * qcom,port-config =
+ * <group port prealloc react ceil weight
+ * res_off res_ceil dynamic>;
+ */
+ qcom,port-config = <0 0 12 40 30 7 5 20 1>,
+ <0 1 12 40 30 7 5 20 1>,
+ <0 2 12 40 30 7 5 20 1>,
+ <0 3 12 40 30 7 5 20 1>,
+ <0 4 12 40 30 7 5 20 1>,
+ <0 5 12 40 30 7 5 20 1>,
+ <0 6 12 40 30 7 5 20 1>,
+ <0 7 12 40 30 7 5 20 1>,
+ <0 8 12 128 48 7 5 20 1>,
+ <0 9 12 128 48 7 5 20 1>;
+ };
+
+ queue-management-config {
+ /*
+ * qcom,group-config =
+ * <group total prealloc ceil resume_off>;
+ */
+ qcom,group-config = <0 500 0 0 0>;
+ /*
+ * qcom,queue-config =
+ * <queue_base queue_num group prealloc ceil
+ * weight resume_off dynamic>;
+ */
+ qcom,queue-config = <0 256 0 0 50 5 18 1>,
+ <256 44 0 0 50 0 18 0>;
+ };
+
+ port-scheduler-resource {
+ port0 {
+ port-id = <0>;
+ qcom,ucast-queue = <0 63>;
+ qcom,mcast-queue = <256 263>;
+ qcom,l0sp = <0 0>;
+ qcom,l0cdrr = <0 7>;
+ qcom,l0edrr = <0 7>;
+ qcom,l1cdrr = <0 0>;
+ qcom,l1edrr = <0 0>;
+ };
+
+ port1 {
+ port-id = <1>;
+ qcom,ucast-queue = <204 211>;
+ qcom,mcast-queue = <272 275>;
+ qcom,l0sp = <51 52>;
+ qcom,l0cdrr = <108 115>;
+ qcom,l0edrr = <108 115>;
+ qcom,l1cdrr = <23 24>;
+ qcom,l1edrr = <23 24>;
+ };
+
+ port2 {
+ port-id = <2>;
+ qcom,ucast-queue = <212 219>;
+ qcom,mcast-queue = <276 279>;
+ qcom,l0sp = <53 54>;
+ qcom,l0cdrr = <116 123>;
+ qcom,l0edrr = <116 123>;
+ qcom,l1cdrr = <25 26>;
+ qcom,l1edrr = <25 26>;
+ };
+ };
+
+ port-scheduler-config {
+ port0 {
+ port-id = <0>;
+ l1scheduler {
+ group0 {
+ /* flow ID from L0 SP */
+ qcom,flow = <0>;
+ /* sp cpri cdrr epri edrr */
+ qcom,scheduler-config = <0 0 0 0 0>;
+ };
+ };
+
+ l0scheduler {
+ group0 {
+ /* unicast queue */
+ qcom,ucast-queue = <0>;
+ qcom,ucast-loop-priority = <8>;
+ /* multicast queue */
+ qcom,mcast-queue = <256>;
+ /* sp cpri cdrr epri edrr */
+ qcom,scheduler-config = <0 0 0 0 0>;
+ };
+
+ group1 {
+ qcom,ucast-queue = <8>;
+ qcom,ucast-loop-priority = <8>;
+ qcom,mcast-queue = <257>;
+ qcom,scheduler-config = <0 0 0 0 0>;
+ };
+
+ group2 {
+ qcom,ucast-queue = <16>;
+ qcom,ucast-loop-priority = <8>;
+ qcom,mcast-queue = <258>;
+ qcom,scheduler-config = <0 0 0 0 0>;
+ };
+
+ group3 {
+ qcom,ucast-queue = <24>;
+ qcom,ucast-loop-priority = <8>;
+ qcom,mcast-queue = <259>;
+ qcom,scheduler-config = <0 0 0 0 0>;
+ };
+
+ group4 {
+ qcom,ucast-queue = <32>;
+ qcom,ucast-loop-priority = <8>;
+ qcom,mcast-queue = <260>;
+ qcom,scheduler-config = <0 0 0 0 0>;
+ };
+
+ group5 {
+ qcom,ucast-queue = <40>;
+ qcom,ucast-loop-priority = <8>;
+ qcom,mcast-queue = <261>;
+ qcom,scheduler-config = <0 0 0 0 0>;
+ };
+
+ group6 {
+ qcom,ucast-queue = <48>;
+ qcom,ucast-loop-priority = <8>;
+ qcom,mcast-queue = <262>;
+ qcom,scheduler-config = <0 0 0 0 0>;
+ };
+
+ group7 {
+ qcom,ucast-queue = <56>;
+ qcom,ucast-loop-priority = <8>;
+ qcom,mcast-queue = <263>;
+ qcom,scheduler-config = <0 0 0 0 0>;
+ };
+ };
+ };
+
+ port1 {
+ port-id = <1>;
+ l1scheduler {
+ group0 {
+ qcom,flow = <51>;
+ qcom,flow-loop-priority = <2>;
+ qcom,scheduler-config = <1 0 23 0 23>;
+ };
+ };
+
+ l0scheduler {
+ group0 {
+ qcom,ucast-queue = <204>;
+ qcom,ucast-loop-priority = <8>;
+ /* max priority per SP */
+ qcom,drr-max-priority = <4>;
+ qcom,mcast-queue = <272>;
+ qcom,mcast-loop-priority = <4>;
+ qcom,scheduler-config = <51 0 108 0 108>;
+ };
+ };
+ };
+
+ port2 {
+ port-id = <2>;
+ l1scheduler {
+ group0 {
+ qcom,flow = <53>;
+ qcom,flow-loop-priority = <2>;
+ qcom,scheduler-config = <2 0 25 0 25>;
+ };
+ };
+
+ l0scheduler {
+ group0 {
+ qcom,ucast-queue = <212>;
+ qcom,ucast-loop-priority = <8>;
+ /* max priority per SP */
+ qcom,drr-max-priority = <4>;
+ qcom,mcast-queue = <276>;
+ qcom,mcast-loop-priority = <4>;
+ qcom,scheduler-config = <53 0 116 0 116>;
+ };
+ };
+ };
+ };
+ };
};
timer {