From patchwork Wed Jan 10 10:25:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dharma Balasubiramani X-Patchwork-Id: 186778 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2411:b0:101:2151:f287 with SMTP id m17csp704865dyi; Wed, 10 Jan 2024 02:39:19 -0800 (PST) X-Google-Smtp-Source: AGHT+IE7DKeJfqNM7viI9NP+NfAVucmr4LCy3G/AWxwf71c3CtEb3einKUwLC1z7WXYjTZz5lmGp X-Received: by 2002:a05:6358:9193:b0:174:e47a:f4b3 with SMTP id j19-20020a056358919300b00174e47af4b3mr851582rwa.13.1704883159323; Wed, 10 Jan 2024 02:39:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704883159; cv=none; d=google.com; s=arc-20160816; b=oBzC+QuxnzzV16AOS/V/NPqi/BniagTyliyQujmdVGrf1XAQP9ZDL0MlaXUxKa9jMq 8WpiQP/YdxA4yo5RGmgr3v1w5yxug3CsBraUb3JLkqD+gU7zEOqsD3iHg2DcRy/Ok0ND dhvfsjXuQNJNC/yRzLQXbDGgAqBCdqHKDq1wv8mNL6G5lAeVmzDhx0dcYeJkcbvHb8Br wYI3HLIhYJA/wOn+l8o08VYT8YBm3hAyO+tBxYhh3mZ5pMEKb1KlhVyoMK93SA2RhOk7 qCFLAi98tqmiy0OiqeQzPijKpuBFL1M+Cgcabi83tpUHAlrNwRxidoCQYR8+sS9xZao2 miQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=L5QyxPqEt+HiRViusXh0leWQQL0t3rVwhW62WrWQP1w=; fh=9cDuyv/ey+sB27DsOJniAhB4tstbmI9RK35MY8bd5X0=; b=iaWsn/Kap9jBP2XgPjr9m77SiDM8nXQnJXlpvJMX/jmxl+t9qguuH4tWqXsi6YSMop Fznerkf0dsiTmkYubqBC74NQL5mJXwGp4HiSvkKugT0yhj+mMmhuL5AbH7QIhVjIQ2D9 QH6UP64JaCHVqsPbl1xfyWbb9FwZVzeiMbxGFI0/KYF34aJHFq0pqw4hUxqTc7RF7W42 Dv5FVuhzo9lfR1sbz0FoamurJlVCQzTLuBsk4Ey08kfL+/nCGwUvAalbMNGyzgeEjOxt P3FfmMn+vzCkK8HXwgg3wjwrOIHuItZjwKc/QyLiRv90UMHTax7WtaMePzoltpARyi7Q W5dw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=QMRWzH1e; spf=pass (google.com: domain of linux-kernel+bounces-21994-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-21994-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=REJECT dis=NONE) header.from=microchip.com Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. [2604:1380:40f1:3f00::1]) by mx.google.com with ESMTPS id v5-20020a655685000000b005cec91fa47csi3208351pgs.680.2024.01.10.02.39.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 02:39:19 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-21994-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) client-ip=2604:1380:40f1:3f00::1; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=QMRWzH1e; spf=pass (google.com: domain of linux-kernel+bounces-21994-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-21994-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=REJECT dis=NONE) header.from=microchip.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sy.mirrors.kernel.org (Postfix) with ESMTPS id 2646FB27EEB for ; Wed, 10 Jan 2024 10:30:05 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BAEB147F5A; Wed, 10 Jan 2024 10:26:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="QMRWzH1e" Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB2C046BA6; Wed, 10 Jan 2024 10:26:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1704882399; x=1736418399; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5WUd7zZW6vaz2VFpcySRfwde2JHnsfcvgGymaZA0H0s=; b=QMRWzH1e9gW+jYSuJIF5GsdSF5RBrlor7KuSCb0kOw6fIqNq8uSVkzSu 1Y/90fiPzybFg++BmPNYwWkFlmNzmrBIY98uCXc4dFXrPlpGQDyK8ZAqD URLReSa7ZeG2AUSbczMvjmsb2PM6Eomr7k4ge3FIYTfGbxvO+GLcYLshb pxoHJpZSeuDLdiNUie/M4qswfkkX/b/OjSzfyTlvqII6yytoFXvW6ROPk 3x6sS8Sql1A5kGo8/g4hNQUYkDAKjNCHqAjZxW7rx2J2LTBrjtjc8TA3P yrtMOPgIq5At0KhdnYHa+C6mGI9hOg1FXQTyWk33DV4YHI4LWWEulQuVK w==; X-CSE-ConnectionGUID: 5D2eo3saR72tqfGaKhDyVQ== X-CSE-MsgGUID: P1+T+hWdTWqrrzrBB18h6g== X-ThreatScanner-Verdict: Negative X-IronPort-AV: E=Sophos;i="6.04,184,1695711600"; d="scan'208";a="14511322" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Jan 2024 03:26:35 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 10 Jan 2024 03:26:25 -0700 Received: from che-lt-i70843lx.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 10 Jan 2024 03:26:17 -0700 From: Dharma Balasubiramani To: , , , , , , , , , , , , , , , , , , , , CC: Dharma Balasubiramani Subject: [PATCH 3/3] dt-bindings: atmel,hlcdc: convert pwm bindings to json-schema Date: Wed, 10 Jan 2024 15:55:35 +0530 Message-ID: <20240110102535.246177-4-dharma.b@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240110102535.246177-1-dharma.b@microchip.com> References: <20240110102535.246177-1-dharma.b@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787699563595007320 X-GMAIL-MSGID: 1787699563595007320 Convert device tree bindings for Atmel's HLCDC PWM controller to YAML format. Signed-off-by: Dharma Balasubiramani --- .../bindings/pwm/atmel,hlcdc-pwm.yaml | 62 +++++++++++++++++++ .../bindings/pwm/atmel-hlcdc-pwm.txt | 29 --------- 2 files changed, 62 insertions(+), 29 deletions(-) create mode 100644 Documentation/devicetree/bindings/pwm/atmel,hlcdc-pwm.yaml delete mode 100644 Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt diff --git a/Documentation/devicetree/bindings/pwm/atmel,hlcdc-pwm.yaml b/Documentation/devicetree/bindings/pwm/atmel,hlcdc-pwm.yaml new file mode 100644 index 000000000000..99eaad55ccb3 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/atmel,hlcdc-pwm.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2024 Microchip Technology, Inc. and its subsidiaries +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/atmel,hlcdc-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel's HLCDC (High-end LCD Controller) PWM driver + +maintainers: + - Nicolas Ferre + - Alexandre Belloni + - Claudiu Beznea + +description: | + Device-Tree bindings for Atmel's HLCDC PWM driver. The Atmel HLCDC PWM is a + subdevice of the HLCDC MFD device. + # See ../mfd/atmel,hlcdc.yaml for more details. + +properties: + compatible: + const: atmel,hlcdc-pwm + + pinctrl-names: + const: default + + pinctrl-0: true + + "#pwm-cells": + const: 3 + description: | + This PWM chip uses the default 3 cells bindings defined in pwm.yaml in + this directory. + +required: + - compatible + - pinctrl-names + - pinctrl-0 + - "#pwm-cells" + +additionalProperties: false + +examples: + - | + #include + #include + #include + + hlcdc: hlcdc@f0030000 { + compatible = "atmel,sama5d3-hlcdc"; + reg = <0xf0030000 0x2000>; + clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clock-names = "periph_clk","sys_clk", "slow_clk"; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; + + hlcdc_pwm: hlcdc-pwm { + compatible = "atmel,hlcdc-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_pwm>; + #pwm-cells = <3>; + }; + }; diff --git a/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt b/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt deleted file mode 100644 index afa501bf7f94..000000000000 --- a/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt +++ /dev/null @@ -1,29 +0,0 @@ -Device-Tree bindings for Atmel's HLCDC (High-end LCD Controller) PWM driver - -The Atmel HLCDC PWM is subdevice of the HLCDC MFD device. -See ../mfd/atmel-hlcdc.txt for more details. - -Required properties: - - compatible: value should be one of the following: - "atmel,hlcdc-pwm" - - pinctr-names: the pin control state names. Should contain "default". - - pinctrl-0: should contain the pinctrl states described by pinctrl - default. - - #pwm-cells: should be set to 3. This PWM chip use the default 3 cells - bindings defined in pwm.yaml in this directory. - -Example: - - hlcdc: hlcdc@f0030000 { - compatible = "atmel,sama5d3-hlcdc"; - reg = <0xf0030000 0x2000>; - clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; - clock-names = "periph_clk","sys_clk", "slow_clk"; - - hlcdc_pwm: hlcdc-pwm { - compatible = "atmel,hlcdc-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_pwm>; - #pwm-cells = <3>; - }; - };