Message ID | 20240109192310.16234-3-bwicaksono@nvidia.com |
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State | New |
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Tue, 9 Jan 2024 11:24:28 -0800 From: Besar Wicaksono <bwicaksono@nvidia.com> To: <acme@redhat.com>, <catalin.marinas@arm.com>, <will@kernel.org>, <john.g.garry@oracle.com>, <james.clark@arm.com>, <mike.leach@linaro.org>, <peterz@infradead.org>, <mingo@redhat.com>, <mark.rutland@arm.com>, <alexander.shishkin@linux.intel.com>, <jolsa@kernel.org>, <namhyung@kernel.org>, <irogers@google.com>, <alisaidi@amazon.com>, <vsethi@nvidia.com>, <rwiley@nvidia.com>, <ywan@nvidia.com> CC: <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-perf-users@vger.kernel.org>, <linux-tegra@vger.kernel.org>, <treding@nvidia.com>, <jonathanh@nvidia.com>, Besar Wicaksono <bwicaksono@nvidia.com> Subject: [PATCH v1 2/3] tools headers arm64: Add Neoverse-V2 part Date: Tue, 9 Jan 2024 13:23:09 -0600 Message-ID: <20240109192310.16234-3-bwicaksono@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240109192310.16234-1-bwicaksono@nvidia.com> References: <20240109192310.16234-1-bwicaksono@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: <linux-kernel.vger.kernel.org> List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989EA:EE_|DM4PR12MB5167:EE_ X-MS-Office365-Filtering-Correlation-Id: 6d711796-81e1-4173-62b9-08dc1148a520 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Series |
arm64: Support Neoverse-V2 for Perf Arm SPE
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Commit Message
Besar Wicaksono
Jan. 9, 2024, 7:23 p.m. UTC
Add the part number and MIDR for Neoverse-V2.
Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com>
---
tools/arch/arm64/include/asm/cputype.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tools/arch/arm64/include/asm/cputype.h b/tools/arch/arm64/include/asm/cputype.h index 7c7493cb571f..fe13a25fa082 100644 --- a/tools/arch/arm64/include/asm/cputype.h +++ b/tools/arch/arm64/include/asm/cputype.h @@ -85,6 +85,7 @@ #define ARM_CPU_PART_CORTEX_X2 0xD48 #define ARM_CPU_PART_NEOVERSE_N2 0xD49 #define ARM_CPU_PART_CORTEX_A78C 0xD4B +#define ARM_CPU_PART_NEOVERSE_V2 0xD4F #define APM_CPU_PART_XGENE 0x000 #define APM_CPU_VAR_POTENZA 0x00 @@ -156,6 +157,7 @@ #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) +#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)