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Tue, 9 Jan 2024 11:24:08 -0800 From: Besar Wicaksono To: , , , , , , , , , , , , , , , , CC: , , , , , , Besar Wicaksono Subject: [PATCH v1 1/3] arm64: Add Neoverse-V2 part Date: Tue, 9 Jan 2024 13:23:08 -0600 Message-ID: <20240109192310.16234-2-bwicaksono@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240109192310.16234-1-bwicaksono@nvidia.com> References: <20240109192310.16234-1-bwicaksono@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C7:EE_|DM6PR12MB4370:EE_ X-MS-Office365-Filtering-Correlation-Id: 1666ad53-a8b3-428c-d65b-08dc11489bd7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: MC28ZejVDVqkw9nRk+GGmIQqsYYfmLgEyOCu9u+iBlWb7uPfMLqRfAZKOwm8UI3vu8pj1L4Os/JTW5iMTDDgo/ocY5RAyCaTidOidJdcrnTMQ3zFD+WIMuyWBylHEjUd0E87L5/nOvEeAWhbjIariKzPmMx8C6qrZT0Dn3sxZJAvnjtwB3pZUcneGb7qCta6cSlINxmyQ75B4xjgc4qTDmZM7HJbcRn94yqSGbZtksVEPPLo2ENStzGD1VLRxesy+RzNc8VokqmwG694+OuJZEB84f08zXdQ6ed9FmFGOpGbqWUCCIb9ZirL5q4VJv9sFqnSDJYjYtdjZojDKaiUVjRtiya2MnpgMXdG5ovsxBUGemegfATglH0KaS6txZPORB+v1ZKgCiUSEJT2+3kpm7DatGqh1Ltk5tqO+SJcxPGFjBBtdFXkCNWUXFoKVwWBrk38zZ7o6cqqj3Y+iRGg3smLJOVfksj+8QG2UtDn14+SoCQ1ha7CArlzZBsLRY3tMNop3ZTU1OC8ntD5Thl45eK33TBTOHkegTjiyqlTGitMFSYT0A0joXOEJn+rcavyCn+3BW+IQ6IzWPRYR3dah3/ONzJvA/3XxEMKvjYAu2pFRMd3g5M5i4QoKwdrhnJweBwkkgR1cuMMugejChM2sF9pv1pZPIdPdnCwuapk/oSTq8l7mGVcGBeDGpGWPbB4nSIDGbiH8KjCEGovuQP2TnxCUvu3EQgeXXZparr81Dpd1R8NUSDqGunxNJ+c6atf4c3eXWlIMPTK36CrJ5Lt9DlU4AYOf4G8rlAYev2VnUZVXSo88ji3GCs0rzArxvg1 X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(376002)(39860400002)(346002)(136003)(396003)(230922051799003)(1800799012)(186009)(82310400011)(64100799003)(451199024)(46966006)(36840700001)(40470700004)(26005)(2616005)(1076003)(336012)(426003)(478600001)(7696005)(47076005)(107886003)(316002)(5660300002)(41300700001)(7416002)(2906002)(70586007)(6636002)(70206006)(110136005)(54906003)(4326008)(8676002)(8936002)(356005)(921011)(82740400003)(36860700001)(36756003)(7636003)(86362001)(40460700003)(40480700001)(2101003)(83996005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jan 2024 19:24:32.8292 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1666ad53-a8b3-428c-d65b-08dc11489bd7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4370 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787642064646657624 X-GMAIL-MSGID: 1787642064646657624 Add the part number and MIDR for Neoverse-V2 Signed-off-by: Besar Wicaksono --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 7c7493cb571f..fe13a25fa082 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -85,6 +85,7 @@ #define ARM_CPU_PART_CORTEX_X2 0xD48 #define ARM_CPU_PART_NEOVERSE_N2 0xD49 #define ARM_CPU_PART_CORTEX_A78C 0xD4B +#define ARM_CPU_PART_NEOVERSE_V2 0xD4F #define APM_CPU_PART_XGENE 0x000 #define APM_CPU_VAR_POTENZA 0x00 @@ -156,6 +157,7 @@ #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) +#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)