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[147.75.199.223]) by mx.google.com with ESMTPS id n13-20020a05622a040d00b0042979913212si6567577qtx.454.2024.01.08.01.05.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jan 2024 01:05:00 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-19223-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) client-ip=147.75.199.223; Authentication-Results: mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=K4BsnmzL; spf=pass (google.com: domain of linux-kernel+bounces-19223-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-19223-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id 44D731C22B17 for ; Mon, 8 Jan 2024 08:59:32 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A17F413FF9; Mon, 8 Jan 2024 08:58:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b="K4BsnmzL" X-Original-To: linux-kernel@vger.kernel.org Received: from mail.fris.de (mail.fris.de [116.203.77.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3DDA0E543; Mon, 8 Jan 2024 08:58:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fris.de Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id A1246C00F6; Mon, 8 Jan 2024 09:51:16 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1704703877; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=akNdEaX30HzkHKP9IaufaAprUiB8tYROpt6AP/lowi0=; b=K4BsnmzL+Kuq5/Qqu0wqe9rMKbqqu1F81mBa60iTXsSP2dLjqr1aWoEkd7BGz+EWvZiUts 7EKCFBGLq+qnAUcEVoeiOds+dFAToqV07+u26TLGK0IweTryL0ZsfXskWAG66mOB5qsmzz jwFMBG35c7Q4bhzMknigiPVicy7fDD5c8BC8Xe4uN7gnTAAhOQ6I+pfYO8EFa/ZHLGk4xM rgDVv3KndMnMGmE8awsSuGeGzyrSBZkHMGDbchqO560Z3VzjfWFvpKvhfwsW31c8NgJZVq LK5wWCHdjb7r+/Tbjw7fBWzAp/ImYUuSZPmEmtDSbHB9DwwGgzIixdBJpKoBig== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Frieder Schrempf , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Fabio Estevam , Krzysztof Kozlowski , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v4 04/12] arm64: dts: imx8mm-kontron: Disable pullups for onboard UART signals on BL board Date: Mon, 8 Jan 2024 09:49:01 +0100 Message-ID: <20240108084945.75356-5-frieder@fris.de> In-Reply-To: <20240108084945.75356-1-frieder@fris.de> References: <20240108084945.75356-1-frieder@fris.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787512435710610821 X-GMAIL-MSGID: 1787512435710610821 From: Frieder Schrempf These signals are actively driven by the SoC or by the onboard transceiver. There's no need to enable the internal pull resistors and due to silicon errata ERR050080 let's disable the internal ones to prevent any unwanted behavior in case they wear out. Fixes: 8668d8b2e67f ("arm64: dts: Add the Kontron i.MX8M Mini SoMs and baseboards") Signed-off-by: Frieder Schrempf --- Changes for v3: * none Changes for v2: * none --- .../boot/dts/freescale/imx8mm-kontron-bl.dts | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts index 5fd2e45258b11..ee93db11c0d06 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts @@ -292,19 +292,19 @@ MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19 pinctrl_uart1: uart1grp { fsl,pins = < - MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140 - MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140 - MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140 + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x0 + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x0 + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x0 + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x0 >; }; pinctrl_uart2: uart2grp { fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 - MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 - MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x0 + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x0 + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x0 + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x0 >; };