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(fttx-pool-157.180.226.237.bambit.de [157.180.226.237]) by mxbox2.masterlogin.de (Postfix) with ESMTPSA id 8391B1007EB; Thu, 4 Jan 2024 17:39:46 +0000 (UTC) From: Frank Wunderlich To: linux-mediatek@lists.infradead.org Cc: Frank Wunderlich , Michael Turquette , Stephen Boyd , Matthias Brugger , AngeloGioacchino Del Regno , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sam Shih , Daniel Golle , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH 2/2] clk: mediatek: add infracfg reset controller for mt7988 Date: Thu, 4 Jan 2024 18:39:30 +0100 Message-Id: <20240104173930.13907-3-linux@fw-web.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240104173930.13907-1-linux@fw-web.de> References: <20240104173930.13907-1-linux@fw-web.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Mail-ID: 6d201640-91c2-4ac9-a649-d071cf765a5b X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787182881218790099 X-GMAIL-MSGID: 1787182881218790099 From: Frank Wunderlich Infracfg can also operate as reset controller, add support for it. Signed-off-by: Frank Wunderlich --- drivers/clk/mediatek/clk-mt7988-infracfg.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt7988-infracfg.c b/drivers/clk/mediatek/clk-mt7988-infracfg.c index 8011ef278bea..1660a45349ff 100644 --- a/drivers/clk/mediatek/clk-mt7988-infracfg.c +++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c @@ -14,6 +14,9 @@ #include "clk-gate.h" #include "clk-mux.h" #include +#include + +#define INFRA_RST_SET_OFFSET 0x80 static DEFINE_SPINLOCK(mt7988_clk_lock); @@ -249,12 +252,29 @@ static const struct mtk_gate infra_clks[] = { GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", "sysaxi_sel", 31), }; +static u16 infra_rst_ofs[] = { + INFRA_RST_SET_OFFSET, +}; + +static u16 infra_idx_map[] = { + [MT7988_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 9, +}; + +static struct mtk_clk_rst_desc infra_rst_desc = { + .version = MTK_RST_SET_CLR, + .rst_bank_ofs = infra_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(infra_rst_ofs), + .rst_idx_map = infra_idx_map, + .rst_idx_map_nr = ARRAY_SIZE(infra_idx_map), +}; + static const struct mtk_clk_desc infra_desc = { .clks = infra_clks, .num_clks = ARRAY_SIZE(infra_clks), .mux_clks = infra_muxes, .num_mux_clks = ARRAY_SIZE(infra_muxes), .clk_lock = &mt7988_clk_lock, + .rst_desc = &infra_rst_desc, }; static const struct of_device_id of_match_clk_mt7988_infracfg[] = {