[v7,02/16] PCI: imx6: Simplify phy handling by using by using IMX6_PCIE_FLAG_HAS_PHY
Message ID | 20231227182727.1747435-3-Frank.Li@nxp.com |
---|---|
State | New |
Headers |
Return-Path: <linux-kernel+bounces-12198-ouuuleilei=gmail.com@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp1599103dyb; Wed, 27 Dec 2023 10:28:47 -0800 (PST) X-Google-Smtp-Source: AGHT+IHlLBOUHECevBqnDqNY/NCyXPtJWDcGw+Pf/nhGZ4dvHxYpRAeBuLDBvOJ213d/aPRk7Gcf X-Received: by 2002:ad4:5963:0:b0:67f:43f8:cc6f with SMTP id eq3-20020ad45963000000b0067f43f8cc6fmr16343294qvb.61.1703701727703; Wed, 27 Dec 2023 10:28:47 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1703701727; cv=pass; d=google.com; s=arc-20160816; b=hQEritpV7oLIl7VePEgsJzmT+opetjb9KZi/FwYs5gzU6LUoi/qPhA16P2UDX+J62r tu+a4P/wlaBaPhBRi/H2zElQxF3pk+QYrLw7sA7Rk/QerjkoKYb5M7bTd6g94rcV8hLz yoKQ4FDtkBmuvq8YGtSuqOlV9MjctNG1bPDYwZAKZnnLiC6HdoI7wHjEYYCjlbxaP/hY SRwQ2/a/v/9c1V3bHI0sleTQUuG1C8VBLLLgzAo0miegsD7PXGlHaJkKMpdyPjEsGaX4 L44agtjXZ8yfAWlefFZ/NsV0uzT+3Cxrh3a2Ug3riBx/NH8pWQi0Xk+YAwqPbnH7D0Vw AYAg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:list-unsubscribe:list-subscribe:list-id:precedence :content-transfer-encoding:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=Mwdd+DiAZ3s7dB+tmBXPZ8hiA83HBFxwkXxyNbl3QHM=; fh=492Ek0Vpabbqz4y1lk9p/Id6JH5wlBXcD/z8VK8wbWM=; b=TUlg3E81EnFH/3IQt0ARDAE5jF3C+k5dhc4rXdmfJaWx5dUuYVJGsaaQO6TixqnDgg 4t9DqbQA7Eg8kexPl38DgwLk0jYan0f2cviL2yUNLYV0Mem9aeyI5Iz4fYryRaEKu7J7 ZEx1W16090tNg4wi3jPR7M0+F/gAVDmyUKymb7bpDui/4/ItK9dQ96/vEpj/tJlwSVp5 H9Fk4sflc08ZhoqG6LfrZWCnYfYlZ3dgv5lrSREaH6aGIJBJeL84ZDjFd9w/Ir2bo+wG 7/NK70SC2bnDY6GKDv8ExwqX0Ek16VlbtUPsc9RbUVSh5nYexV4GswWbVtARcZ0aaOns CaDA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=ZbBE7JFV; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel+bounces-12198-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-12198-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. [2604:1380:45d1:ec00::1]) by mx.google.com with ESMTPS id gy13-20020a056214242d00b0068059cc9998si2081533qvb.481.2023.12.27.10.28.47 for <ouuuleilei@gmail.com> (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Dec 2023 10:28:47 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-12198-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1; Authentication-Results: mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=ZbBE7JFV; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel+bounces-12198-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-12198-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id 6BF301C21A3D for <ouuuleilei@gmail.com>; Wed, 27 Dec 2023 18:28:47 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9656E47F70; Wed, 27 Dec 2023 18:28:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b="ZbBE7JFV" X-Original-To: linux-kernel@vger.kernel.org Received: from EUR04-HE1-obe.outbound.protection.outlook.com (mail-he1eur04on2059.outbound.protection.outlook.com [40.107.7.59]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 521C547F59; Wed, 27 Dec 2023 18:28:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=A/wrnYWzBXWArttmvLKxi3yRDPvMvNmH6aFUMr/tuY8pGg5+fmamknEns2yn8xYVNdN42PZ4rRUfpDRdjjedqfvmtct6+IPhJ2uNj5TUBJc1yJ9JjPKFlSPO3AasLYm4C3p1TklRpk3musbsiX/RIxd5RIHoW5KaL2KziK3/wl5o54lJJU1WAI/sDxiJEFgNpSpwEdELtfZY5MlxL15/mlafSKMiuG2rdyCHcWROdojLswhEecdWJN+FLSOKftpITNxlxdE7TteBbduQq2TYj0dQMS2mgoW8z7PDNiUhKaBRVTcejEHK76j2Qw/0rsr7CGwRE/3tJekBsbH+qW60xw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Mwdd+DiAZ3s7dB+tmBXPZ8hiA83HBFxwkXxyNbl3QHM=; b=b5ChtR1ensu6ie9S2Rtxwls6LsbYghP6BPoJnGouwBu6zitLBT7H6AY+JI++rU+cC6zYyjXCsGA6QuNIwe2rA5W+UeW92kR2tR9ywXWhST9rzhQILbw+yep95fJdykJujv97S8Qh6TBn43wZEeRiaBfLVMgK7z1NdZ/AR+Q8qmstpN19ueJGpzccOHcoIrBz+V2UBwe++ZAfjZAaESX84ot2V0q3kZB5BItGGd22VO/x9khjOdPSez/QkSZypeelu2tjHVbCHsrUBJOif/XyDxzifpA5jKu5fMnapidpvHaut/RLb+3MXIPWvXXwN32bplHa1m3HAGntsmGvOY2mBA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Mwdd+DiAZ3s7dB+tmBXPZ8hiA83HBFxwkXxyNbl3QHM=; b=ZbBE7JFVhJO6wGoMxXxHklAOobo1bWHxn90SPuTnbIzYSt+AtpA0ydbzybcbKl6Vk5ZKlbaus3k4c+0cVRqsBoPfcFXfCPSIWukE1shUuTMbfdMwNFOTDKVkaOeuIs5vxVRgz/WCdEIrP/+iCGPY3vHO+PWtzxmRfk4UQn0uUb0= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by DU2PR04MB9050.eurprd04.prod.outlook.com (2603:10a6:10:2e5::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7113.27; Wed, 27 Dec 2023 18:28:00 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40%7]) with mapi id 15.20.7113.027; Wed, 27 Dec 2023 18:28:00 +0000 From: Frank Li <Frank.Li@nxp.com> To: krzysztof.kozlowski@linaro.org Cc: Frank.Li@nxp.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: [PATCH v7 02/16] PCI: imx6: Simplify phy handling by using by using IMX6_PCIE_FLAG_HAS_PHY Date: Wed, 27 Dec 2023 13:27:13 -0500 Message-Id: <20231227182727.1747435-3-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231227182727.1747435-1-Frank.Li@nxp.com> References: <20231227182727.1747435-1-Frank.Li@nxp.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SJ2PR07CA0018.namprd07.prod.outlook.com (2603:10b6:a03:505::22) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: <linux-kernel.vger.kernel.org> List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org> MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|DU2PR04MB9050:EE_ X-MS-Office365-Filtering-Correlation-Id: 4433da78-0951-4cd1-87ad-08dc07098e0f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: XLi/DPC1XElr3fbE0kfERG/bgWdJKYvwq8lBke83xcuAItwq9fg2h3QGHWNP3xBTW4yDTpRz35D11Qo0SuYDLH7L6dLOGT21pPf1TFgkiScMpAqNBiaqYyxe5ctSAGMA7ugHnrMOAZgnind4IDO4GAt24IxCCa/Ji1InFdg8Yul6gA4OIoBWZO7MUvBclpM+wjzmCLsoqoUW5EwjufEJ65MXw0Gx+wP9aCqT7TXj+vv7NB7BG3lZQHzaMMoaXgwgj2D8Tfm76muy2m+QK2YBmnic0LVUD/gHCY20DbtvgqzauAS4ohhuTksBRL9V3d2pBqw4F50rm+fCcJZ63pPPjWaMTT9qPfUDBGiCY3PyJp8pvp8ehZ5gwEhDF5YJKi22ePT1RzBrA4CeqdY35Hg/q7VJGGHSrmfO+eI1aIZ/kbPcovWiXTI0PHzPoNh5gnpNetMVPNORvuU/C+Trchax/Tf7iNsuPordq3xXqd2pehwU/aBp96IbRKW0+/fPBs/LYGppMGrTCgoxU+hc4sBrTCpS/falRil377PgS4Qyl/VLUpgtyQT02p8vL/uhseaQpsYP64n5oV++LJUFPY1UfxhC2da0J3xvVHERGMy1PYU9io8UImOKiH/URLwKNRr9 X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:AM6PR04MB4838.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(396003)(366004)(136003)(376002)(39860400002)(346002)(230922051799003)(64100799003)(451199024)(1800799012)(186009)(5660300002)(2906002)(7416002)(478600001)(38100700002)(2616005)(26005)(52116002)(1076003)(6486002)(41300700001)(36756003)(86362001)(38350700005)(66556008)(316002)(66476007)(66946007)(6916009)(6666004)(6512007)(8676002)(4326008)(8936002)(6506007)(83380400001);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: BtAvRiQxKoFsrNlmQVrWDWVlNRAghzmNOKZGha45FySnZUFBQuv0Nd6tElAU2xGaNdQicM015Y4vEmkWCeq/YjWG3DU/1MDi/4gHBiy7R9TA3yjJ2qyPPDr+AtHURqgh5M4JWaEF5/rZ9sLddhAGLQWxbBPzE4vlNbdn6Vk9uJ2YeHyPzBI9wTB4uDvHLYkLPpPVHPnLCnLLgL8NVfa1SxS1tsVuDUnUm8AloPY5hyfikMeaRLkAGH4zDh2o1QIX+Yp3iU3A/f3mXZQOZcAbseO61bGE02OBuACKNQrfzjhsq5AC7umR6pNPLuAbNXcr4kYITHIz9WKLkfW7nRJB7N/nSPkJffYftnpS5Sz986PpkLkrzfVopUukRWdhIzJWsE/MzZL7+lyAOIWL4wwGIalreOhK7LYCsy/Q6bcbEMFssCjCZjFondSJeA888pYG+PFXdqP47qbBFtNLUFpyzb2l+3d/87EGPTCh8FRdJOhsDwlnLS7jlTIThb94Ev4rn+ha+jrGJfW342T0iTwuzYy8S2HVoF78Wkp9rFHDQf8isey/eJFLLnvGri7O5DczgS4yGnSHPVfhnYVSzaAgXfeE/hYvoUIZ8EfEOkD531B0956v0Gn1SkgXanwCkUxExhs5Uk8rK3eX7q0QHxrT8YduaKwojGRSmFvXlYykSSU+F3I6d8BIgPmTVD2tl9bqqTx5inJoH0uIjokf6SIexbK1z6LBdu2gTN4K4tcQA7//52cOHNvQR3xoYKe/aba2cawFjo2yOsA6/TzFazTzrQEMx8+9i95FDCscoAmpD4TytG+tlZwdVuW8dVJwzWbrHOIC6EQcxAGjdyfPuX4fWDjQCecaGsBsSRGwtPg0wgFOsxG3Xl26nKeDH5Q+SwBnr8wwQ7D5RYrGqnjHpG/gX3fLGkV/ypR+Khs2FX6U1fFuowfFjybAWrsDkt7JikNYdWUevh4DO1QadllhiOvtvgV3gQzEtwjesXvkej5rp8jHuRKHcd72dlWOCOE6l5skmGj8FW4P4YJla+S72mWjIArF29ljejdPkzccplUFQD9HOIZiEBZYenbeNp/Qv9F+XJyJ9fVBIDy2w3pfsu1Klwx+4xXd2ChMqda+5itbYVY0u/OPKip2g1qFJgYRuPJJDrDmlukoC+qUIcRZ0dDeqtyyK3YbE053Vy4RmZKlryIpyOtDKnFCmLp2vrgXB+mZguE8nM2NAQislGg44yf0ySuczmdI+6iqV7DnadZ0XmmfKURciCIC0ziSGUdU9iZNe9hq85HpAlRJZ2WKwJXYStAITGZQEWTMDp6f9L2t2fzhB+4qwgi2eMS5Izu9y8oMLG8RfB1054nFq/UTg6n8YRelNAsbBhyxZPRMqCcd1zvsiXbGo25bykjX6ZYB0A5zu5LLwp/2uX/OnEVUQLHZcuryCZgCyWeG8mBjtL9aLQvI1CsEX14HEhjCX2qVupQXYjT7MsF2KpV5O8ZrRRtlNk6a2VjCHU+JXtVX6W7WYejkGMJUmOH87o4VX4C1SA+lLxeYhC6gmcsPQZ1bRRcTWpQd4Cr9oQ//YfK03Eyu7Lc= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4433da78-0951-4cd1-87ad-08dc07098e0f X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4838.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Dec 2023 18:28:00.1915 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: u0VLNrNOedlG1hJFrvsJ1sZxbdLxrn2ocsaeElti/S3dbI1734rtSJTspIG5AW7JE5l+49YqASU9V1LqLeMNSA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR04MB9050 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1786460742674223412 X-GMAIL-MSGID: 1786460742674223412 |
Series |
PCI: imx6: Clean up and add imx95 pci support
|
|
Commit Message
Frank Li
Dec. 27, 2023, 6:27 p.m. UTC
Refactors the phy handling logic in the imx6 PCI driver by adding
IMX6_PCIE_FLAG_HAS_PHY bitmask define for drvdata::flags.
The drvdata::flags and a bitmask ensures a cleaner and more scalable
switch-case structure for handling phy.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
Notes:
Change from v4 to v5:
- none, Keep IMX6_PCIE_FLAG_HAS_PHY to indicate dts mismatch when platform
require phy suppport.
Change from v1 to v3:
- none
drivers/pci/controller/dwc/pci-imx6.c | 23 ++++++++++++++++-------
1 file changed, 16 insertions(+), 7 deletions(-)
Comments
On Wed, Dec 27, 2023 at 01:27:13PM -0500, Frank Li wrote: > Refactors the phy handling logic in the imx6 PCI driver by adding > IMX6_PCIE_FLAG_HAS_PHY bitmask define for drvdata::flags. > > The drvdata::flags and a bitmask ensures a cleaner and more scalable > switch-case structure for handling phy. > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > --- > > Notes: > Change from v4 to v5: > - none, Keep IMX6_PCIE_FLAG_HAS_PHY to indicate dts mismatch when platform > require phy suppport. > > Change from v1 to v3: > - none > > drivers/pci/controller/dwc/pci-imx6.c | 23 ++++++++++++++++------- > 1 file changed, 16 insertions(+), 7 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index 50d9faaa17f71..4d620249f3d52 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -60,6 +60,9 @@ enum imx6_pcie_variants { > #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) > #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1) > #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) > +#define IMX6_PCIE_FLAG_HAS_PHY BIT(3) Every PCIe setup requires PHY for its operation. Perhaps you are referring to external PHY? If so, please rename this to IMX6_PCIE_FLAG_HAS_EXT_PHY. > + > +#define imx6_check_flag(pci, val) (pci->drvdata->flags & val) > > #define IMX6_PCIE_MAX_CLKS 6 > > @@ -1277,6 +1280,13 @@ static int imx6_pcie_probe(struct platform_device *pdev) > if (ret) > return ret; > > + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHY)) { IMO, we would not need these kind of checks in the driver if the DT binding is properly validated using schema. But folks always want to validate "broken DT" in the drivers :( But I'm fine with this check for now since not everyone agree with above. - Mani > + imx6_pcie->phy = devm_phy_get(dev, "pcie-phy"); > + if (IS_ERR(imx6_pcie->phy)) > + return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy), > + "failed to get pcie phy\n"); > + } > + > switch (imx6_pcie->drvdata->variant) { > case IMX7D: > if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) > @@ -1306,11 +1316,6 @@ static int imx6_pcie_probe(struct platform_device *pdev) > return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset), > "failed to get pcie apps reset control\n"); > > - imx6_pcie->phy = devm_phy_get(dev, "pcie-phy"); > - if (IS_ERR(imx6_pcie->phy)) > - return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy), > - "failed to get pcie phy\n"); > - > break; > default: > break; > @@ -1444,13 +1449,15 @@ static const struct imx6_pcie_drvdata drvdata[] = { > }, > [IMX8MM] = { > .variant = IMX8MM, > - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, > + .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | > + IMX6_PCIE_FLAG_HAS_PHY, > .gpr = "fsl,imx8mm-iomuxc-gpr", > .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, > }, > [IMX8MP] = { > .variant = IMX8MP, > - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, > + .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | > + IMX6_PCIE_FLAG_HAS_PHY, > .gpr = "fsl,imx8mp-iomuxc-gpr", > .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, > }, > @@ -1462,12 +1469,14 @@ static const struct imx6_pcie_drvdata drvdata[] = { > }, > [IMX8MM_EP] = { > .variant = IMX8MM_EP, > + .flags = IMX6_PCIE_FLAG_HAS_PHY, > .mode = DW_PCIE_EP_TYPE, > .gpr = "fsl,imx8mm-iomuxc-gpr", > .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, > }, > [IMX8MP_EP] = { > .variant = IMX8MP_EP, > + .flags = IMX6_PCIE_FLAG_HAS_PHY, > .mode = DW_PCIE_EP_TYPE, > .gpr = "fsl,imx8mp-iomuxc-gpr", > .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, > -- > 2.34.1 >
On Sat, Jan 06, 2024 at 09:03:23PM +0530, Manivannan Sadhasivam wrote: > On Wed, Dec 27, 2023 at 01:27:13PM -0500, Frank Li wrote: > > Refactors the phy handling logic in the imx6 PCI driver by adding > > IMX6_PCIE_FLAG_HAS_PHY bitmask define for drvdata::flags. > > > > The drvdata::flags and a bitmask ensures a cleaner and more scalable > > switch-case structure for handling phy. > > > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > > --- > > > > Notes: > > Change from v4 to v5: > > - none, Keep IMX6_PCIE_FLAG_HAS_PHY to indicate dts mismatch when platform > > require phy suppport. > > > > Change from v1 to v3: > > - none > > > > drivers/pci/controller/dwc/pci-imx6.c | 23 ++++++++++++++++------- > > 1 file changed, 16 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > > index 50d9faaa17f71..4d620249f3d52 100644 > > --- a/drivers/pci/controller/dwc/pci-imx6.c > > +++ b/drivers/pci/controller/dwc/pci-imx6.c > > @@ -60,6 +60,9 @@ enum imx6_pcie_variants { > > #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) > > #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1) > > #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) > > +#define IMX6_PCIE_FLAG_HAS_PHY BIT(3) > > Every PCIe setup requires PHY for its operation. Perhaps you are referring to > external PHY? If so, please rename this to IMX6_PCIE_FLAG_HAS_EXT_PHY. Actually, it means use phy driver. How about using IMX6_PCIE_HAS_PHYDRV? > > > + > > +#define imx6_check_flag(pci, val) (pci->drvdata->flags & val) > > > > #define IMX6_PCIE_MAX_CLKS 6 > > > > @@ -1277,6 +1280,13 @@ static int imx6_pcie_probe(struct platform_device *pdev) > > if (ret) > > return ret; > > > > + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHY)) { > > IMO, we would not need these kind of checks in the driver if the DT binding is > properly validated using schema. But folks always want to validate "broken DT" > in the drivers :( > > But I'm fine with this check for now since not everyone agree with above. > > - Mani > > > + imx6_pcie->phy = devm_phy_get(dev, "pcie-phy"); > > + if (IS_ERR(imx6_pcie->phy)) > > + return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy), > > + "failed to get pcie phy\n"); > > + } > > + > > switch (imx6_pcie->drvdata->variant) { > > case IMX7D: > > if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) > > @@ -1306,11 +1316,6 @@ static int imx6_pcie_probe(struct platform_device *pdev) > > return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset), > > "failed to get pcie apps reset control\n"); > > > > - imx6_pcie->phy = devm_phy_get(dev, "pcie-phy"); > > - if (IS_ERR(imx6_pcie->phy)) > > - return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy), > > - "failed to get pcie phy\n"); > > - > > break; > > default: > > break; > > @@ -1444,13 +1449,15 @@ static const struct imx6_pcie_drvdata drvdata[] = { > > }, > > [IMX8MM] = { > > .variant = IMX8MM, > > - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, > > + .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | > > + IMX6_PCIE_FLAG_HAS_PHY, > > .gpr = "fsl,imx8mm-iomuxc-gpr", > > .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, > > }, > > [IMX8MP] = { > > .variant = IMX8MP, > > - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, > > + .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | > > + IMX6_PCIE_FLAG_HAS_PHY, > > .gpr = "fsl,imx8mp-iomuxc-gpr", > > .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, > > }, > > @@ -1462,12 +1469,14 @@ static const struct imx6_pcie_drvdata drvdata[] = { > > }, > > [IMX8MM_EP] = { > > .variant = IMX8MM_EP, > > + .flags = IMX6_PCIE_FLAG_HAS_PHY, > > .mode = DW_PCIE_EP_TYPE, > > .gpr = "fsl,imx8mm-iomuxc-gpr", > > .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, > > }, > > [IMX8MP_EP] = { > > .variant = IMX8MP_EP, > > + .flags = IMX6_PCIE_FLAG_HAS_PHY, > > .mode = DW_PCIE_EP_TYPE, > > .gpr = "fsl,imx8mp-iomuxc-gpr", > > .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, > > -- > > 2.34.1 > > > > -- > மணிவண்ணன் சதாசிவம்
On Sat, Jan 06, 2024 at 11:50:28AM -0500, Frank Li wrote: > On Sat, Jan 06, 2024 at 09:03:23PM +0530, Manivannan Sadhasivam wrote: > > On Wed, Dec 27, 2023 at 01:27:13PM -0500, Frank Li wrote: > > > Refactors the phy handling logic in the imx6 PCI driver by adding > > > IMX6_PCIE_FLAG_HAS_PHY bitmask define for drvdata::flags. > > > > > > The drvdata::flags and a bitmask ensures a cleaner and more scalable > > > switch-case structure for handling phy. > > > > > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > > > --- > > > > > > Notes: > > > Change from v4 to v5: > > > - none, Keep IMX6_PCIE_FLAG_HAS_PHY to indicate dts mismatch when platform > > > require phy suppport. > > > > > > Change from v1 to v3: > > > - none > > > > > > drivers/pci/controller/dwc/pci-imx6.c | 23 ++++++++++++++++------- > > > 1 file changed, 16 insertions(+), 7 deletions(-) > > > > > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > > > index 50d9faaa17f71..4d620249f3d52 100644 > > > --- a/drivers/pci/controller/dwc/pci-imx6.c > > > +++ b/drivers/pci/controller/dwc/pci-imx6.c > > > @@ -60,6 +60,9 @@ enum imx6_pcie_variants { > > > #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) > > > #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1) > > > #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) > > > +#define IMX6_PCIE_FLAG_HAS_PHY BIT(3) > > > > Every PCIe setup requires PHY for its operation. Perhaps you are referring to > > external PHY? If so, please rename this to IMX6_PCIE_FLAG_HAS_EXT_PHY. > > Actually, it means use phy driver. How about using IMX6_PCIE_HAS_PHYDRV? > Ah, ok. Yes, this makes sense. - Mani > > > > > + > > > +#define imx6_check_flag(pci, val) (pci->drvdata->flags & val) > > > > > > #define IMX6_PCIE_MAX_CLKS 6 > > > > > > @@ -1277,6 +1280,13 @@ static int imx6_pcie_probe(struct platform_device *pdev) > > > if (ret) > > > return ret; > > > > > > + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHY)) { > > > > IMO, we would not need these kind of checks in the driver if the DT binding is > > properly validated using schema. But folks always want to validate "broken DT" > > in the drivers :( > > > > But I'm fine with this check for now since not everyone agree with above. > > > > - Mani > > > > > + imx6_pcie->phy = devm_phy_get(dev, "pcie-phy"); > > > + if (IS_ERR(imx6_pcie->phy)) > > > + return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy), > > > + "failed to get pcie phy\n"); > > > + } > > > + > > > switch (imx6_pcie->drvdata->variant) { > > > case IMX7D: > > > if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) > > > @@ -1306,11 +1316,6 @@ static int imx6_pcie_probe(struct platform_device *pdev) > > > return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset), > > > "failed to get pcie apps reset control\n"); > > > > > > - imx6_pcie->phy = devm_phy_get(dev, "pcie-phy"); > > > - if (IS_ERR(imx6_pcie->phy)) > > > - return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy), > > > - "failed to get pcie phy\n"); > > > - > > > break; > > > default: > > > break; > > > @@ -1444,13 +1449,15 @@ static const struct imx6_pcie_drvdata drvdata[] = { > > > }, > > > [IMX8MM] = { > > > .variant = IMX8MM, > > > - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, > > > + .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | > > > + IMX6_PCIE_FLAG_HAS_PHY, > > > .gpr = "fsl,imx8mm-iomuxc-gpr", > > > .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, > > > }, > > > [IMX8MP] = { > > > .variant = IMX8MP, > > > - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, > > > + .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | > > > + IMX6_PCIE_FLAG_HAS_PHY, > > > .gpr = "fsl,imx8mp-iomuxc-gpr", > > > .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, > > > }, > > > @@ -1462,12 +1469,14 @@ static const struct imx6_pcie_drvdata drvdata[] = { > > > }, > > > [IMX8MM_EP] = { > > > .variant = IMX8MM_EP, > > > + .flags = IMX6_PCIE_FLAG_HAS_PHY, > > > .mode = DW_PCIE_EP_TYPE, > > > .gpr = "fsl,imx8mm-iomuxc-gpr", > > > .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, > > > }, > > > [IMX8MP_EP] = { > > > .variant = IMX8MP_EP, > > > + .flags = IMX6_PCIE_FLAG_HAS_PHY, > > > .mode = DW_PCIE_EP_TYPE, > > > .gpr = "fsl,imx8mp-iomuxc-gpr", > > > .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, > > > -- > > > 2.34.1 > > > > > > > -- > > மணிவண்ணன் சதாசிவம்
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 50d9faaa17f71..4d620249f3d52 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -60,6 +60,9 @@ enum imx6_pcie_variants { #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1) #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) +#define IMX6_PCIE_FLAG_HAS_PHY BIT(3) + +#define imx6_check_flag(pci, val) (pci->drvdata->flags & val) #define IMX6_PCIE_MAX_CLKS 6 @@ -1277,6 +1280,13 @@ static int imx6_pcie_probe(struct platform_device *pdev) if (ret) return ret; + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHY)) { + imx6_pcie->phy = devm_phy_get(dev, "pcie-phy"); + if (IS_ERR(imx6_pcie->phy)) + return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy), + "failed to get pcie phy\n"); + } + switch (imx6_pcie->drvdata->variant) { case IMX7D: if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) @@ -1306,11 +1316,6 @@ static int imx6_pcie_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset), "failed to get pcie apps reset control\n"); - imx6_pcie->phy = devm_phy_get(dev, "pcie-phy"); - if (IS_ERR(imx6_pcie->phy)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy), - "failed to get pcie phy\n"); - break; default: break; @@ -1444,13 +1449,15 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX8MM] = { .variant = IMX8MM, - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, + .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | + IMX6_PCIE_FLAG_HAS_PHY, .gpr = "fsl,imx8mm-iomuxc-gpr", .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, }, [IMX8MP] = { .variant = IMX8MP, - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, + .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | + IMX6_PCIE_FLAG_HAS_PHY, .gpr = "fsl,imx8mp-iomuxc-gpr", .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, }, @@ -1462,12 +1469,14 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX8MM_EP] = { .variant = IMX8MM_EP, + .flags = IMX6_PCIE_FLAG_HAS_PHY, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mm-iomuxc-gpr", .clk_names = {"pcie_bus", "pcie", "pcie_aux"}, }, [IMX8MP_EP] = { .variant = IMX8MP_EP, + .flags = IMX6_PCIE_FLAG_HAS_PHY, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mp-iomuxc-gpr", .clk_names = {"pcie_bus", "pcie", "pcie_aux"},