| Message ID | 20231220165423.v2.5.I8249df4df0b7d12fb68ea1e69f84ca589c574bb1@changeid |
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From: Mark Hasemeyer <markhas@chromium.org>
To: LKML <linux-kernel@vger.kernel.org>
Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
Tzung-Bi Shih <tzungbi@kernel.org>,
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Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org
Subject: [PATCH v2 05/22] ARM: dts: rockchip: rk3288: Enable cros-ec-spi as
wake source
Date: Wed, 20 Dec 2023 16:54:19 -0700
Message-ID:
<20231220165423.v2.5.I8249df4df0b7d12fb68ea1e69f84ca589c574bb1@changeid>
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| Series |
Improve IRQ wake capability reporting and update the cros_ec driver to use it
|
|
Commit Message
Mark Hasemeyer
Dec. 20, 2023, 11:54 p.m. UTC
The cros_ec driver currently assumes that cros-ec-spi compatible device
nodes are a wakeup-source even though the wakeup-source property is not
defined.
Add the wakeup-source property to all cros-ec-spi compatible device
nodes to match expected behavior.
Signed-off-by: Mark Hasemeyer <markhas@chromium.org>
---
Changes in v2:
-Split by arch/soc
arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi index 092316be67f74..1554fe36e60fe 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi @@ -112,6 +112,7 @@ cros_ec: ec@0 { pinctrl-names = "default"; pinctrl-0 = <&ec_int>; spi-max-frequency = <3000000>; + wakeup-source; i2c_tunnel: i2c-tunnel { compatible = "google,cros-ec-i2c-tunnel";