Message ID | 20231220151358.2147066-16-nikunj@amd.com |
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State | New |
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Add Secure TSC support for SNP guests
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Commit Message
Nikunj A. Dadhania
Dec. 20, 2023, 3:13 p.m. UTC
When SecureTSC is enabled and TscInvariant (bit 8) in CPUID_8000_0007_edx is set, kernel complains with the below firmware bug: [Firmware Bug]: TSC doesn't count with P0 frequency! Secure TSC need not run at P0 frequency, the TSC frequency is set by the VMM as part of the SNP_LAUNCH_START command. Avoid the check when Secure TSC is enabled Signed-off-by: Nikunj A Dadhania <nikunj@amd.com> Tested-by: Peter Gonda <pgonda@google.com> --- arch/x86/kernel/cpu/amd.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index f322ebd053a9..b4a19e3fda8d 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -551,7 +551,8 @@ static void early_init_amd_mc(struct cpuinfo_x86 *c) static void bsp_init_amd(struct cpuinfo_x86 *c) { - if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { + if (cpu_has(c, X86_FEATURE_CONSTANT_TSC) && + !cpu_feature_enabled(X86_FEATURE_SNP_SECURE_TSC)) { if (c->x86 > 0x10 || (c->x86 == 0x10 && c->x86_model >= 0x2)) {