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Fri, 15 Dec 2023 03:15:56 -0800 (PST) Received: from localhost.localdomain ([5.133.47.210]) by smtp.gmail.com with ESMTPSA id g13-20020a056000118d00b003333d46a9e8sm18511497wrx.56.2023.12.15.03.15.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Dec 2023 03:15:56 -0800 (PST) From: srinivas.kandagatla@linaro.org To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org, Patrick Delaunay , Srinivas Kandagatla Subject: [PATCH 10/10] nvmem: stm32: add support for STM32MP25 BSEC to control OTP data Date: Fri, 15 Dec 2023 11:15:36 +0000 Message-Id: <20231215111536.316972-11-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231215111536.316972-1-srinivas.kandagatla@linaro.org> References: <20231215111536.316972-1-srinivas.kandagatla@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2231; i=srinivas.kandagatla@linaro.org; h=from:subject; bh=4O4WBaJhnw+j/8i/dvSP/B2/3NEdWuXi4KfR7fhrYm0=; b=owEBbQGS/pANAwAKAXqh/VnHNFU3AcsmYgBlfDVYlyX1V5fA3OGAmnHqciQ/gqZpouklcrtwJ uWQX60PZ+OJATMEAAEKAB0WIQQi509axvzi9vce3Y16of1ZxzRVNwUCZXw1WAAKCRB6of1ZxzRV NwCBB/0SEYgVT+0cRSdc9Epo1PpmIEag/pDdzgwIBM7Y49/eIwUxUHZN1AHyQqaW3is6i2iO4FN ChjUjrnd1gIkmbfDobB6DuY+9QW00GNjg4kcDixxYmO1+Rk646SJrnacW2vSmtQtQzU+82rOGKm GVto3RE5tbDUcMqTQVyOlX2DLkPtKGJs6QeEFFOdn6CSV8nTTfndNuZZuxdo2VFCMIkTGnKZcFP kygxBPd3YSzbSaT0BiyHAhnPdjipqhNbOLJo2ExboZ3m2bakxdOjRs/XfobPC6dSfUtpcS8/lvl mgxkX8TUosjv+bi43X6jmqA8iR0pXJ23u4G+Tnm09iel+NYb X-Developer-Key: i=srinivas.kandagatla@linaro.org; a=openpgp; fpr=ED6472765AB36EC43B3EF97AD77E3FC0562560D6 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785346504680436470 X-GMAIL-MSGID: 1785346504680436470 From: Patrick Delaunay On STM32MP25, OTP area may be read/written by using BSEC (boot, security and OTP control). The BSEC internal peripheral is only managed by the secure world. The 12 Kbits of OTP (effective) are organized into the following regions: - lower OTP (OTP0 to OTP127) = 4096 lower OTP bits, bitwise (1-bit) programmable - mid OTP (OTP128 to OTP255) = 4096 middle OTP bits, bulk (32-bit) programmable - upper OTP (OTP256 to OTP383) = 4096 upper OTP bits, bulk (32-bit) programmable, only accessible when BSEC is in closed state. As HWKEY and ECIES key are only accessible by ROM code; only 368 OTP words are managed in this driver (OTP0 to OTP267). This patch adds the STM32MP25 configuration for reading and writing the OTP data using the OP-TEE BSEC TA services. Signed-off-by: Patrick Delaunay Signed-off-by: Srinivas Kandagatla --- drivers/nvmem/stm32-romem.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/nvmem/stm32-romem.c b/drivers/nvmem/stm32-romem.c index 8a553b1799a8..82879b1c9eb9 100644 --- a/drivers/nvmem/stm32-romem.c +++ b/drivers/nvmem/stm32-romem.c @@ -269,6 +269,19 @@ static const struct stm32_romem_cfg stm32mp13_bsec_cfg = { .ta = true, }; +/* + * STM32MP25 BSEC OTP: 3 regions of 32-bits data words + * lower OTP (OTP0 to OTP127), bitwise (1-bit) programmable + * mid OTP (OTP128 to OTP255), bulk (32-bit) programmable + * upper OTP (OTP256 to OTP383), bulk (32-bit) programmable + * but no access to HWKEY and ECIES key: limited at OTP367 + */ +static const struct stm32_romem_cfg stm32mp25_bsec_cfg = { + .size = 368 * 4, + .lower = 127, + .ta = true, +}; + static const struct of_device_id stm32_romem_of_match[] __maybe_unused = { { .compatible = "st,stm32f4-otp", }, { .compatible = "st,stm32mp15-bsec", @@ -276,6 +289,9 @@ static const struct of_device_id stm32_romem_of_match[] __maybe_unused = { }, { .compatible = "st,stm32mp13-bsec", .data = (void *)&stm32mp13_bsec_cfg, + }, { + .compatible = "st,stm32mp25-bsec", + .data = (void *)&stm32mp25_bsec_cfg, }, { /* sentinel */ }, };