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Thu, 14 Dec 2023 15:13:56 -0600 From: Ben Levinsky To: , , CC: , , Subject: [PATCH 3/3] mailbox: zynqmp: Enable Bufferless IPI usage on Versal-based SOC's Date: Thu, 14 Dec 2023 13:13:54 -0800 Message-ID: <20231214211354.348294-4-ben.levinsky@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231214211354.348294-1-ben.levinsky@amd.com> References: <20231214211354.348294-1-ben.levinsky@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0E3:EE_|IA0PR12MB8973:EE_ X-MS-Office365-Filtering-Correlation-Id: ca005360-5db6-43bb-7ebf-08dbfce9960a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: zAWpzFKYQ9IPyt3HH0GF7pJIGvuGA99D3H9LNqbRtPs+RpdydEp0uBG3t/t0s0U8A3LA72LFTWJOl2TUvtz8ktpy06PEvV5WJHWH6zF3Tr3hmRS+W5bHygk5XMusmAyUqLJIkdlToTtBhk8ZlWEnFAUGscuhZ9cLKR6GGhQ8anxNM66Ayo0afoPoJitzWepzGvAqCrcisbGjOSoAbue1y20e1CWAkIy91saVGN6g5Wf4hFYefXkUvikWJZS1lvDpsSjKPwWDbdGqnzW5Z1UBZmfG8Rj3eXWL0GqrgxpoQRrtniNeP/W9v2peCUuDDSokmHE6kG7J6afOExbMsyz5qnHTExOE9Dgwj3Hohc/8fjmgEJu9uQe33RsupulL+KDB2GO0dKyL94kPiwlxLMdWdn9Sa1igC8T60eFtGoatbqiOMynb3JQSKCYb4KBKQR20U3MkpiZpwr5ahjfJy6wA4/5Ayr7EAEibR3IRCZWKQ0YVbfREsAy2kkf70cBuRBVe1uc/1JbW9fnpT+Ox/+2s37W3MG0Wm/2b8vsxIwGgOHTwta0qoKJGQTjWhCJIBxelR5m1PtoNdP2g7n8JB4ECZ8raihINFa+Cq/A4Y8G1i3Xz6kLuGpSeTUC6cfwmgX6fbmzQAWLNgV3HO447IqImIMYCjRjS83a7L3leAqvs6qoRrD7y/IVcdxDU2q4a5mW6WINUHTKa2A3sAdbnVn3MLQn/a8OAPTFNETg4PItdOfx5+x7O+lU8g5bS2JEL/Vjg3FgEo6w7A3N8EBeqCJCektfaNGAjsvpXqnqTc9sUGUo= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(39860400002)(376002)(346002)(136003)(230922051799003)(186009)(82310400011)(451199024)(64100799003)(1800799012)(40470700004)(36840700001)(46966006)(41300700001)(15650500001)(2906002)(44832011)(5660300002)(40460700003)(36860700001)(82740400003)(81166007)(356005)(70206006)(70586007)(54906003)(6636002)(426003)(40480700001)(43170500006)(336012)(26005)(110136005)(83380400001)(316002)(2616005)(36756003)(1076003)(86362001)(966005)(478600001)(47076005)(8936002)(4326008)(8676002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Dec 2023 21:13:57.7438 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ca005360-5db6-43bb-7ebf-08dbfce9960a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E3.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8973 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785293464703229537 X-GMAIL-MSGID: 1785293464703229537 On Xilinx-AMD Versal and Versal-NET, there exist both inter-processor-interrupts with corresponding message buffers and without such buffers. Add a routine that, if the corresponding DT compatible string "xlnx,versal-ipi-mailbox" is used then a Versal-based SOC can use a mailbox Device Tree entry where both host and remote can use either of the buffered or bufferless interrupts. Signed-off-by: Ben Levinsky --- Note that the linked patch provides corresponding bindings. Depends on: https://lore.kernel.org/all/20231214054224.957336-3-tanmay.shah@amd.com/T/ --- drivers/mailbox/zynqmp-ipi-mailbox.c | 146 +++++++++++++++++++++++++-- 1 file changed, 139 insertions(+), 7 deletions(-) diff --git a/drivers/mailbox/zynqmp-ipi-mailbox.c b/drivers/mailbox/zynqmp-ipi-mailbox.c index edefb80a6e47..316d9406064e 100644 --- a/drivers/mailbox/zynqmp-ipi-mailbox.c +++ b/drivers/mailbox/zynqmp-ipi-mailbox.c @@ -52,6 +52,13 @@ #define IPI_MB_CHNL_TX 0 /* IPI mailbox TX channel */ #define IPI_MB_CHNL_RX 1 /* IPI mailbox RX channel */ +/* IPI Message Buffer Information */ +#define RESP_OFFSET 0x20U +#define DEST_OFFSET 0x40U +#define IPI_BUF_SIZE 0x20U +#define DST_BIT_POS 9U +#define SRC_BITMASK GENMASK(11, 8) + /** * struct zynqmp_ipi_mchan - Description of a Xilinx ZynqMP IPI mailbox channel * @is_opened: indicate if the IPI channel is opened @@ -170,9 +177,11 @@ static irqreturn_t zynqmp_ipi_interrupt(int irq, void *data) if (ret > 0 && ret & IPI_MB_STATUS_RECV_PENDING) { if (mchan->is_opened) { msg = mchan->rx_buf; - msg->len = mchan->req_buf_size; - memcpy_fromio(msg->data, mchan->req_buf, - msg->len); + if (msg) { + msg->len = mchan->req_buf_size; + memcpy_fromio(msg->data, mchan->req_buf, + msg->len); + } mbox_chan_received_data(chan, (void *)msg); status = IRQ_HANDLED; } @@ -282,26 +291,26 @@ static int zynqmp_ipi_send_data(struct mbox_chan *chan, void *data) if (mchan->chan_type == IPI_MB_CHNL_TX) { /* Send request message */ - if (msg && msg->len > mchan->req_buf_size) { + if (msg && msg->len > mchan->req_buf_size && mchan->req_buf) { dev_err(dev, "channel %d message length %u > max %lu\n", mchan->chan_type, (unsigned int)msg->len, mchan->req_buf_size); return -EINVAL; } - if (msg && msg->len) + if (msg && msg->len && mchan->req_buf) memcpy_toio(mchan->req_buf, msg->data, msg->len); /* Kick IPI mailbox to send message */ arg0 = SMC_IPI_MAILBOX_NOTIFY; zynqmp_ipi_fw_call(ipi_mbox, arg0, 0, &res); } else { /* Send response message */ - if (msg && msg->len > mchan->resp_buf_size) { + if (msg && msg->len > mchan->resp_buf_size && mchan->resp_buf) { dev_err(dev, "channel %d message length %u > max %lu\n", mchan->chan_type, (unsigned int)msg->len, mchan->resp_buf_size); return -EINVAL; } - if (msg && msg->len) + if (msg && msg->len && mchan->resp_buf) memcpy_toio(mchan->resp_buf, msg->data, msg->len); arg0 = SMC_IPI_MAILBOX_ACK; zynqmp_ipi_fw_call(ipi_mbox, arg0, IPI_SMC_ACK_EIRQ_MASK, @@ -640,6 +649,126 @@ static int zynqmp_ipi_setup(struct zynqmp_ipi_mbox *ipi_mbox, return 0; } +/** + * versal_ipi_setup - Set up IPIs to support mixed usage of + * Buffered and Bufferless IPIs. + * + * @ipi_mbox: pointer to IPI mailbox private data structure + * @node: IPI mailbox device node + * + * Return: 0 for success, negative value for failure + */ +static int versal_ipi_setup(struct zynqmp_ipi_mbox *ipi_mbox, + struct device_node *node) +{ + struct zynqmp_ipi_mchan *tx_mchan, *rx_mchan; + struct resource host_res, remote_res; + struct device_node *parent_node; + int host_idx, remote_idx; + struct device *mdev, *dev; + + tx_mchan = &ipi_mbox->mchans[IPI_MB_CHNL_TX]; + rx_mchan = &ipi_mbox->mchans[IPI_MB_CHNL_RX]; + parent_node = of_get_parent(node); + dev = ipi_mbox->pdata->dev; + mdev = &ipi_mbox->dev; + + host_idx = zynqmp_ipi_mbox_get_buf_res(parent_node, "msg", &host_res); + remote_idx = zynqmp_ipi_mbox_get_buf_res(node, "msg", &remote_res); + + /* + * Only set up buffers if both sides claim to have msg buffers. + * This is because each buffered IPI's corresponding msg buffers + * are reserved for use by other buffered IPI's. + */ + if (!host_idx && !remote_idx) { + u32 host_src, host_dst, remote_src, remote_dst; + u32 buff_sz; + + buff_sz = resource_size(&host_res); + + host_src = host_res.start & SRC_BITMASK; + remote_src = remote_res.start & SRC_BITMASK; + + host_dst = (host_src >> DST_BIT_POS) * DEST_OFFSET; + remote_dst = (remote_src >> DST_BIT_POS) * DEST_OFFSET; + + /* Validate that IPI IDs is within IPI Message buffer space. */ + if (host_dst >= buff_sz || remote_dst >= buff_sz) { + dev_err(mdev, + "Invalid IPI Message buffer values: %x %x\n", + host_dst, remote_dst); + return -EINVAL; + } + + tx_mchan->req_buf = devm_ioremap(mdev, + host_res.start | remote_dst, + IPI_BUF_SIZE); + if (!tx_mchan->req_buf) { + dev_err(mdev, "Unable to map IPI buffer I/O memory\n"); + return -ENOMEM; + } + + tx_mchan->resp_buf = devm_ioremap(mdev, + (remote_res.start | host_dst) + + RESP_OFFSET, IPI_BUF_SIZE); + if (!tx_mchan->resp_buf) { + dev_err(mdev, "Unable to map IPI buffer I/O memory\n"); + return -ENOMEM; + } + + rx_mchan->req_buf = devm_ioremap(mdev, + remote_res.start | host_dst, + IPI_BUF_SIZE); + if (!rx_mchan->req_buf) { + dev_err(mdev, "Unable to map IPI buffer I/O memory\n"); + return -ENOMEM; + } + + rx_mchan->resp_buf = devm_ioremap(mdev, + (host_res.start | remote_dst) + + RESP_OFFSET, IPI_BUF_SIZE); + if (!rx_mchan->resp_buf) { + dev_err(mdev, "Unable to map IPI buffer I/O memory\n"); + return -ENOMEM; + } + + tx_mchan->resp_buf_size = IPI_BUF_SIZE; + tx_mchan->req_buf_size = IPI_BUF_SIZE; + tx_mchan->rx_buf = devm_kzalloc(mdev, IPI_BUF_SIZE + + sizeof(struct zynqmp_ipi_message), + GFP_KERNEL); + if (!tx_mchan->rx_buf) + return -ENOMEM; + + rx_mchan->resp_buf_size = IPI_BUF_SIZE; + rx_mchan->req_buf_size = IPI_BUF_SIZE; + rx_mchan->rx_buf = devm_kzalloc(mdev, IPI_BUF_SIZE + + sizeof(struct zynqmp_ipi_message), + GFP_KERNEL); + if (!rx_mchan->rx_buf) + return -ENOMEM; + } else { + /* + * If here, then set up Bufferless IPI Channel because + * one or both of the IPI's is bufferless. + */ + tx_mchan->req_buf = NULL; + tx_mchan->resp_buf = NULL; + tx_mchan->rx_buf = NULL; + tx_mchan->resp_buf_size = 0; + tx_mchan->req_buf_size = 0; + + rx_mchan->req_buf = NULL; + rx_mchan->resp_buf = NULL; + rx_mchan->rx_buf = NULL; + rx_mchan->resp_buf_size = 0; + rx_mchan->req_buf_size = 0; + } + + return 0; +} + /** * zynqmp_ipi_free_mboxes - Free IPI mailboxes devices * @@ -749,6 +878,9 @@ static const struct of_device_id zynqmp_ipi_of_match[] = { { .compatible = "xlnx,zynqmp-ipi-mailbox", .data = &zynqmp_ipi_setup, }, + { .compatible = "xlnx,versal-ipi-mailbox", + .data = &versal_ipi_setup, + }, {}, }; MODULE_DEVICE_TABLE(of, zynqmp_ipi_of_match);